Lines Matching full:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
90 clocks = <&cru ARMCLKL>;
102 clocks = <&cru ARMCLKL>;
114 clocks = <&cru ARMCLKL>;
126 clocks = <&cru ARMCLKL>;
138 clocks = <&cru ARMCLKB>;
150 clocks = <&cru ARMCLKB>;
182 clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
244 clocks = <&cru ACLK_DMAC0_PERILP>;
255 clocks = <&cru ACLK_DMAC1_PERILP>;
271 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
272 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
293 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
294 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
295 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
296 <&cru SRST_A_PCIE>;
313 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
314 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
315 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
316 <&cru PCLK_GMAC>;
322 resets = <&cru SRST_A_GMAC>;
335 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
336 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
340 resets = <&cru SRST_SDIO0>;
351 assigned-clocks = <&cru HCLK_SD>;
353 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
354 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
358 resets = <&cru SRST_SDMMC>;
368 assigned-clocks = <&cru SCLK_EMMC>;
370 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
386 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
397 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
408 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
419 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
431 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
432 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
433 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
443 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
444 <&cru SCLK_USB3OTG0_SUSPEND>;
446 resets = <&cru SRST_A_USB3_OTG0>;
470 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
471 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
472 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
482 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
483 <&cru SCLK_USB3OTG1_SUSPEND>;
485 resets = <&cru SRST_A_USB3_OTG1>;
506 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
508 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
509 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
513 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
514 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
575 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
577 resets = <&cru SRST_P_SARADC>;
585 assigned-clocks = <&cru SCLK_I2C1>;
587 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
600 assigned-clocks = <&cru SCLK_I2C2>;
602 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
615 assigned-clocks = <&cru SCLK_I2C3>;
617 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
630 assigned-clocks = <&cru SCLK_I2C5>;
632 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
645 assigned-clocks = <&cru SCLK_I2C6>;
647 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
660 assigned-clocks = <&cru SCLK_I2C7>;
662 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
675 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
688 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
701 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
714 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
727 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
742 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
757 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
772 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
787 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
860 assigned-clocks = <&cru SCLK_TSADC>;
862 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
864 resets = <&cru SRST_TSADC>;
1020 clocks = <&cru ACLK_IEP>,
1021 <&cru HCLK_IEP>;
1026 clocks = <&cru ACLK_RGA>,
1027 <&cru HCLK_RGA>;
1033 clocks = <&cru ACLK_VCODEC>,
1034 <&cru HCLK_VCODEC>;
1039 clocks = <&cru ACLK_VDU>,
1040 <&cru HCLK_VDU>;
1048 clocks = <&cru ACLK_GPU>;
1055 clocks = <&cru PCLK_EDP_CTRL>;
1059 clocks = <&cru ACLK_EMMC>;
1064 clocks = <&cru ACLK_GMAC>,
1065 <&cru PCLK_GMAC>;
1072 clocks = <&cru ACLK_PERIHP>;
1080 clocks = <&cru HCLK_SDMMC>,
1081 <&cru SCLK_SDMMC>;
1087 clocks = <&cru HCLK_SDIO>;
1092 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1093 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1097 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1098 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1102 clocks = <&cru ACLK_USB3>;
1113 clocks = <&cru ACLK_HDCP>,
1114 <&cru HCLK_HDCP>,
1115 <&cru PCLK_HDCP>;
1120 clocks = <&cru ACLK_ISP0>,
1121 <&cru HCLK_ISP0>;
1127 clocks = <&cru ACLK_ISP1>,
1128 <&cru HCLK_ISP1>;
1139 clocks = <&cru ACLK_VOP0>,
1140 <&cru HCLK_VOP0>;
1146 clocks = <&cru ACLK_VOP1>,
1147 <&cru HCLK_VOP1>;
1311 clocks = <&cru PCLK_DDR_MON>;
1320 clocks = <&cru SCLK_DDRC>;
1339 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1351 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1353 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1368 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1370 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1385 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1396 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1397 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1409 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1410 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1413 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
1414 <&cru SRST_H_VDU_NOC>, <&cru SRST_A_VDU_NOC>,
1415 <&cru SRST_VDU_CA>, <&cru SRST_VDU_CORE>;
1431 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1444 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1457 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1468 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1470 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1480 clocks = <&cru PCLK_EFUSE1024NS>;
1525 cru: clock-controller@ff760000 { label
1526 compatible = "rockchip,rk3399-cru";
1532 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1533 <&cru PLL_NPLL>,
1534 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1535 <&cru PCLK_PERIHP>,
1536 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1537 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1538 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1539 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1540 <&cru ACLK_GIC_PRE>,
1541 <&cru PCLK_DDR>;
1568 clocks = <&cru SCLK_MIPIDPHY_REF>,
1569 <&cru SCLK_DPHY_RX0_CFG>,
1570 <&cru PCLK_VIO_GRF>;
1580 clocks = <&cru SCLK_USB2PHY0_REF>;
1607 clocks = <&cru SCLK_USB2PHY1_REF>;
1643 clocks = <&cru SCLK_PCIEPHY_REF>;
1646 resets = <&cru SRST_PCIEPHY>;
1659 clocks = <&cru SCLK_PVTM_CORE_L>;
1661 resets = <&cru SRST_PVTM_CORE_L>;
1666 clocks = <&cru SCLK_PVTM_CORE_B>;
1668 resets = <&cru SRST_PVTM_CORE_B>;
1673 clocks = <&cru SCLK_PVTM_DDR>;
1675 resets = <&cru SRST_PVTM_DDR>;
1680 clocks = <&cru SCLK_PVTM_GPU>;
1682 resets = <&cru SRST_PVTM_GPU>;
1691 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1692 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1694 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1697 resets = <&cru SRST_UPHY0>,
1698 <&cru SRST_UPHY0_PIPE_L00>,
1699 <&cru SRST_P_UPHY0_TCPHY>;
1716 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1717 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1719 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1722 resets = <&cru SRST_UPHY1>,
1723 <&cru SRST_UPHY1_PIPE_L00>,
1724 <&cru SRST_P_UPHY1_TCPHY>;
1741 clocks = <&cru PCLK_WDT>;
1749 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1760 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1776 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1777 resets = <&cru SRST_I2S0_8CH>, <&cru SRST_H_I2S0_8CH>;
1793 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1794 resets = <&cru SRST_I2S1_8CH>, <&cru SRST_H_I2S1_8CH>;
1810 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1811 resets = <&cru SRST_I2S2_8CH>, <&cru SRST_H_I2S2_8CH>;
1821 clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
1823 assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
1835 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
1839 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1880 clocks = <&cru SCLK_VOP1_PWM>;
1890 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1905 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
1909 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1950 clocks = <&cru SCLK_VOP0_PWM>;
1960 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1973 clocks = <&cru SCLK_ISP0>,
1974 <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
1975 <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1990 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
2003 clocks = <&cru SCLK_ISP1>,
2004 <&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
2005 <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>,
2006 <&cru PCLK_ISP1_WRAPPER>;
2022 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
2049 clocks = <&cru PCLK_HDMI_CTRL>,
2050 <&cru SCLK_HDMI_SFR>,
2051 <&cru SCLK_HDMI_CEC>,
2052 <&cru PCLK_VIO_GRF>,
2053 <&cru PLL_VPLL>;
2084 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
2085 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
2088 resets = <&cru SRST_P_MIPI_DSI0>;
2120 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
2121 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
2124 resets = <&cru SRST_P_MIPI_DSI1>;
2156 clocks = <&cru SCLK_MIPIDPHY_REF>,
2157 <&cru SCLK_DPHY_TX1RX1_CFG>,
2158 <&cru PCLK_VIO_GRF>,
2159 <&cru PCLK_MIPI_DSI1>;
2171 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
2176 resets = <&cru SRST_P_EDP_CTRL>;
2212 clocks = <&cru ACLK_GPU>;
2344 clocks = <&cru PCLK_GPIO2>;
2357 clocks = <&cru PCLK_GPIO3>;
2370 clocks = <&cru PCLK_GPIO4>;