Lines Matching full:assigned
16 assigned-clocks = <&cru SCLK_EMMC>;
17 assigned-clock-parents = <&cru PLL_GPLL>;
18 assigned-clock-rates = <200000000>;
22 assigned-clocks = <&cru SCLK_UART0_SRC>;
23 assigned-clock-parents = <&cru PLL_GPLL>;
27 assigned-clocks = <&cru SCLK_UART_SRC>;
28 assigned-clock-parents = <&cru PLL_GPLL>;
32 assigned-clocks = <&cru SCLK_UART_SRC>;
33 assigned-clock-parents = <&cru PLL_GPLL>;
37 assigned-clocks = <&cru SCLK_UART_SRC>;
38 assigned-clock-parents = <&cru PLL_GPLL>;
42 assigned-clocks = <&pmucru SCLK_UART4_SRC>;
43 assigned-clock-parents = <&pmucru PLL_PPLL>;
47 assigned-clocks = <&cru SCLK_SPDIF_DIV>;
48 assigned-clock-parents = <&cru PLL_GPLL>;
52 assigned-clocks = <&cru SCLK_I2S0_DIV>;
53 assigned-clock-parents = <&cru PLL_GPLL>;
57 assigned-clocks = <&cru SCLK_I2S1_DIV>;
58 assigned-clock-parents = <&cru PLL_GPLL>;
62 assigned-clocks = <&cru SCLK_I2S2_DIV>;
63 assigned-clock-parents = <&cru PLL_GPLL>;
67 assigned-clocks =
105 assigned-clock-rates =