Lines Matching +full:0 +full:xff3a0000
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
73 reg = <0x0 0x1>;
83 reg = <0x0 0x2>;
93 reg = <0x0 0x3>;
106 arm,psci-suspend-param = <0x0010000>;
123 rockchip,low-temp = <0>;
128 0 1296 50000
136 0 54000 0
145 rockchip,pvtm-ch = <0 0>;
217 rockchip,low-temp = <0>;
222 0 1200 50000
339 rockchip,wake-irq = <0>;
350 #clock-cells = <0>;
359 reg = <0x0 0x110000 0x0 0xf0000>;
365 record-size = <0x0 0x30000>;
366 console-size = <0x0 0xc0000>;
367 ftrace-size = <0x0 0x00000>;
368 pmsg-size = <0x0 0x00000>;
376 pinctrl-0 = <&lcdc_ctl>;
380 #size-cells = <0>;
382 port@0 {
383 reg = <0>;
386 #size-cells = <0>;
388 rgb_in_vop: endpoint@0 {
389 reg = <0>;
404 reg = <0x0 0x0 0x0 0x0>;
412 (0
417 (0
433 #clock-cells = <0>;
440 reg = <0x0 0xff000000 0x0 0x10000>;
455 offset = <0x500>;
468 reg = <0x0 0xff008000 0x0 0x4000>;
474 reg = <0x100 0x10>;
480 #clock-cells = <0>;
489 #phy-cells = <0>;
496 #phy-cells = <0>;
504 reg = <0x0 0xff00b000 0x0 0x1000>;
511 reg = <0x0 0xff00c000 0x0 0x1000>;
524 reg = <0x0 0xff040000 0x0 0x1000>;
529 pinctrl-0 = <&i2c0_xfer>;
531 #size-cells = <0>;
537 reg = <0x0 0xff050000 0x0 0x1000>;
542 pinctrl-0 = <&i2c1_xfer>;
544 #size-cells = <0>;
550 reg = <0x0 0xff060000 0x0 0x1000>;
555 pinctrl-0 = <&i2c2_xfer>;
557 #size-cells = <0>;
563 reg = <0x0 0xff070000 0x0 0x1000>;
568 pinctrl-0 = <&i2c3m0_xfer>;
570 #size-cells = <0>;
576 reg = <0x0 0xff080000 0x0 0x100>;
584 reg = <0x0 0xff0a0000 0x0 0x100>;
593 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
599 reg = <0x0 0xff0b0000 0x0 0x100>;
608 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
614 reg = <0x0 0xff0c0000 0x0 0x100>;
623 pinctrl-0 = <&uart2m0_xfer>;
629 reg = <0x0 0xff0d0000 0x0 0x100>;
638 pinctrl-0 = <&uart3_xfer>;
644 reg = <0x0 0xff0e0000 0x0 0x100>;
653 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
659 reg = <0x0 0xff120000 0x0 0x1000>;
662 #size-cells = <0>;
665 dmas = <&dmac0 0>, <&dmac0 1>;
668 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
675 reg = <0x0 0xff130000 0x0 0x1000>;
678 #size-cells = <0>;
684 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
691 reg = <0x0 0xff140000 0x0 0x1000>;
694 #size-cells = <0>;
700 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
707 reg = <0x0 0xff160000 0x0 0x10>;
712 pinctrl-0 = <&pwm8_pin>;
719 reg = <0x0 0xff160010 0x0 0x10>;
724 pinctrl-0 = <&pwm9_pin>;
731 reg = <0x0 0xff160020 0x0 0x10>;
736 pinctrl-0 = <&pwm10_pin>;
743 reg = <0x0 0xff160030 0x0 0x10>;
748 pinctrl-0 = <&pwm11_pin>;
755 reg = <0x0 0xff170000 0x0 0x10>;
760 pinctrl-0 = <&pwm4_pin>;
767 reg = <0x0 0xff170010 0x0 0x10>;
772 pinctrl-0 = <&pwm5_pin>;
779 reg = <0x0 0xff170020 0x0 0x10>;
784 pinctrl-0 = <&pwm6_pin>;
791 reg = <0x0 0xff170030 0x0 0x10>;
796 pinctrl-0 = <&pwm7_pin>;
803 reg = <0x0 0xff180000 0x0 0x10>;
808 pinctrl-0 = <&pwm0_pin>;
815 reg = <0x0 0xff180010 0x0 0x10>;
820 pinctrl-0 = <&pwm1_pin>;
827 reg = <0x0 0xff180020 0x0 0x10>;
832 pinctrl-0 = <&pwm2_pin>;
839 reg = <0x0 0xff180030 0x0 0x10>;
844 pinctrl-0 = <&pwm3_pin>;
851 reg = <0x0 0xff1a0000 0x0 0x20>;
859 reg = <0x0 0xff1a0020 0x0 0x20>;
868 reg = <0x0 0xff1e0000 0x0 0x100>;
885 thermal-sensors = <&tsadc 0>;
888 threshold: trip-point@0 {
924 reg = <0x0 0xff1f0000 0x0 0x100>;
934 pinctrl-0 = <&tsadc_otp_pin>;
943 reg = <0x0 0xff210000 0x0 0x4000>;
954 reg = <0x07 0x10>;
957 reg = <0x17 0x1>;
960 reg = <0x18 0x1>;
966 reg = <0x0 0xff2c0000 0x0 0x4000>;
967 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
977 reg = <0x0 0xff2d0000 0x0 0x4000>;
988 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>;
998 #size-cells = <0>;
1000 vop_out_rgb: endpoint@0 {
1001 reg = <0>;
1009 reg = <0x0 0xff2f0400 0x0 0x80>;
1025 reg = <0x0 0xff300000 0x0 0x1000>;
1035 dmas = <&dmac1 0>, <&dmac1 1>;
1043 pinctrl-0 = <&i2s_8ch_0_sclktx
1061 reg = <0x0 0xff310000 0x0 0x1000>;
1084 reg = <0x0 0xff320000 0x0 0x1000>;
1106 reg = <0x0 0xff330000 0x0 0x1000>;
1128 reg = <0x0 0xff350000 0x0 0x1000>;
1138 pinctrl-0 = <&i2s_2ch_0_sclk
1147 reg = <0x0 0xff360000 0x0 0x1000>;
1160 reg = <0x0 0xff380000 0x0 0x1000>;
1168 pinctrl-0 = <&pdm_m2_clk
1178 reg = <0x0 0xff3a0000 0x0 0x1000>;
1185 pinctrl-0 = <&spdif_out>;
1191 reg = <0x0 0xff3b0000 0x0 0x1000>;
1200 pinctrl-0 = <&spdif_in>;
1206 reg = <0x0 0xff3c0000 0x0 0x10000>;
1212 rockchip,audio-src = <0>;
1213 rockchip,det-channel = <0>;
1214 rockchip,mode = <0>;
1221 reg = <0x0 0xff400000 0x0 0x40000>;
1236 reg = <0x0 0xff440000 0x0 0x10000>;
1247 reg = <0x0 0xff450000 0x0 0x10000>;
1258 reg = <0x0 0xff480000 0x0 0x4000>;
1264 fifo-depth = <0x100>;
1267 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1273 reg = <0x0 0xff490000 0x0 0x4000>;
1279 fifo-depth = <0x100>;
1286 reg = <0x0 0xff4a0000 0x0 0x4000>;
1292 fifo-depth = <0x100>;
1295 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1302 reg = <0x0 0xff4b0000 0x0 0x4000>;
1308 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
1316 reg = <0x0 0xff4b0000 0x0 0x4000>;
1318 nandc_id = <0>;
1326 reg = <0x0 0xff4e0000 0x0 0x10000>;
1339 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
1348 reg = <0x0 0xff4c0000 0x0 0x4000>;
1359 reg = <0x0 0xff500000 0x0 0x1000>;
1370 reg = <0x0 0xff550000 0x0 0x1000>;
1375 reg = <0x0 0xff560000 0x0 0x10000>;
1392 reg = <0x0 0xff581000 0x0 0x1000>,
1393 <0x0 0xff582000 0x0 0x2000>,
1394 <0x0 0xff584000 0x0 0x2000>,
1395 <0x0 0xff586000 0x0 0x2000>;
1399 #address-cells = <0>;
1404 reg = <0x0 0xfff80000 0x0 0x40000>;
1405 ranges = <0 0x0 0xfff80000 0x40000>;
1410 ddr-sram@0 {
1411 reg = <0x0 0x8000>;
1416 reg = <0x8000 0x38000>;
1436 reg = <0x0 0xff220000 0x0 0x100>;
1447 reg = <0x0 0xff230000 0x0 0x100>;
1458 reg = <0x0 0xff240000 0x0 0x100>;
1469 reg = <0x0 0xff250000 0x0 0x100>;
1480 reg = <0x0 0xff260000 0x0 0x100>;
1572 <0 RK_PB3 2 &pcfg_pull_none>,
1574 <0 RK_PB4 2 &pcfg_pull_none>;
1648 <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
1775 <0 RK_PB3 1 &pcfg_pull_none_smt>,
1776 <0 RK_PB4 1 &pcfg_pull_none_smt>;
1791 <0 RK_PB7 2 &pcfg_pull_none_smt>,
1792 <0 RK_PC0 2 &pcfg_pull_none_smt>;
1813 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1818 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1823 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1828 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1833 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1840 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1845 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1850 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1855 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1860 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1865 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1870 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1875 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1880 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1885 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1890 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1895 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1900 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
2096 <0 RK_PB3 3 &pcfg_pull_none>;
2205 <0 RK_PB5 1 &pcfg_pull_none>;
2210 <0 RK_PB5 1 &pcfg_pull_down>;
2217 <0 RK_PB6 1 &pcfg_pull_none>;
2222 <0 RK_PB6 1 &pcfg_pull_down>;
2229 <0 RK_PB7 1 &pcfg_pull_none>;
2234 <0 RK_PB7 1 &pcfg_pull_down>;
2241 <0 RK_PC0 1 &pcfg_pull_none>;
2246 <0 RK_PC0 1 &pcfg_pull_down>;
2253 <0 RK_PA1 2 &pcfg_pull_none>;
2258 <0 RK_PA1 2 &pcfg_pull_down>;
2265 <0 RK_PC1 2 &pcfg_pull_none>;
2270 <0 RK_PC1 2 &pcfg_pull_down>;
2277 <0 RK_PC2 2 &pcfg_pull_none>;
2282 <0 RK_PC2 2 &pcfg_pull_down>;
2349 <0 RK_PC3 1 &pcfg_pull_none>;
2366 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
2412 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
2417 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
2422 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
2452 <0 RK_PC2 1 &pcfg_pull_none>;
2459 <0 RK_PC1 1 &pcfg_pull_none>;
2620 <0 RK_PB2 0 &pcfg_pull_none>;
2625 <0 RK_PB2 1 &pcfg_pull_none>;
2648 <2 RK_PA3 0 &pcfg_pull_none>;
2697 <0 RK_PC2 3 &pcfg_pull_up>,
2698 <0 RK_PC1 3 &pcfg_pull_up>;
2721 <4 RK_PA7 0 &pcfg_pull_none>;