Lines Matching +full:0 +full:xff3a0000
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
66 reg = <0x0 0x1>;
78 reg = <0x0 0x2>;
90 reg = <0x0 0x3>;
105 arm,psci-suspend-param = <0x0010000>;
114 arm,psci-suspend-param = <0x1010000>;
127 rockchip,low-temp = <0>;
131 0 1512 50000
141 0 13
146 0 50000 0
153 rockchip,pvtm-ch = <0 0>;
253 0 69850 0
262 rockchip,pvtm-ch = <0 0>;
266 rockchip,pvtm-ref-temp = <0>;
267 rockchip,pvtm-temp-prop = <0 0>;
361 bus-id = <0>;
363 enable-msk = <0x40f7>;
368 enable-msk = <0x40bf>;
374 enable-msk = <0x4007>;
423 arm,smc-id = <0x82000010>;
425 #size-cells = <0>;
428 reg = <0x14>;
443 #clock-cells = <0>;
454 rockchip,sleep-debug-en = <0>;
456 (0
465 (0
486 thermal-sensors = <&tsadc 0>;
489 threshold: trip-point-0 {
532 #clock-cells = <0>;
539 #clock-cells = <0>;
546 reg = <0x0 0x0010f000 0x0 0x100>;
551 reg = <0x0 0xff000000 0x0 0x1000>;
557 #size-cells = <0>;
638 reg = <0x0 0xff010000 0x0 0x1000>;
649 offset = <0x200>;
660 #size-cells = <0>;
673 reg = <0x0 0xff030000 0x0 0x100>;
677 dmas = <&dmac 0>, <&dmac 1>;
683 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
689 reg = <0x0 0xff060000 0x0 0x1000>;
700 pinctrl-0 = <&i2s0_8ch_sclktx
717 reg = <0x0 0xff070000 0x0 0x1000>;
724 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
726 #sound-dai-cells = <0>;
732 reg = <0x0 0xff080000 0x0 0x1000>;
739 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
741 #sound-dai-cells = <0>;
747 reg = <0x0 0xff0b0000 0x0 0x400>, <0x0 0xff0b0480 0x0 0x3B80>;
759 reg = <0x0 0xff0b0400 0x0 0x80>;
776 #address-cells = <0>;
778 reg = <0x0 0xff131000 0 0x1000>,
779 <0x0 0xff132000 0 0x2000>,
780 <0x0 0xff134000 0 0x2000>,
781 <0x0 0xff136000 0 0x2000>;
788 reg = <0x0 0xff140000 0x0 0x1000>;
805 #size-cells = <0>;
807 port@0 {
808 reg = <0>;
810 #size-cells = <0>;
812 lvds_vopb_in: endpoint@0 {
813 reg = <0>;
828 pinctrl-0 = <&lcdc_m0_rgb_pins>;
834 #size-cells = <0>;
836 port@0 {
837 reg = <0>;
839 #size-cells = <0>;
841 rgb_in_vopb: endpoint@0 {
842 reg = <0>;
857 reg = <0x0 0xff148000 0x0 0x1000>;
864 #size-cells = <0>;
867 pvtm@0 {
868 reg = <0>;
877 reg = <0x0 0xff158000 0x0 0x100>;
887 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
893 reg = <0x0 0xff160000 0x0 0x100>;
903 pinctrl-0 = <&uart2m0_xfer>;
909 reg = <0x0 0xff168000 0x0 0x100>;
919 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
925 reg = <0x0 0xff170000 0x0 0x100>;
935 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
941 reg = <0x0 0xff178000 0x0 0x100>;
951 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
957 reg = <0x0 0xff180000 0x0 0x1000>;
962 pinctrl-0 = <&i2c0_xfer>;
964 #size-cells = <0>;
970 reg = <0x0 0xff190000 0x0 0x1000>;
975 pinctrl-0 = <&i2c1_xfer>;
977 #size-cells = <0>;
983 reg = <0x0 0xff1a0000 0x0 0x1000>;
988 pinctrl-0 = <&i2c2_xfer>;
990 #size-cells = <0>;
996 reg = <0x0 0xff1b0000 0x0 0x1000>;
1001 pinctrl-0 = <&i2c3_xfer>;
1003 #size-cells = <0>;
1009 reg = <0x0 0xff1d0000 0x0 0x1000>;
1016 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
1018 #size-cells = <0>;
1024 reg = <0x0 0xff1d8000 0x0 0x1000>;
1031 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
1033 #size-cells = <0>;
1039 reg = <0x0 0xff1e0000 0x0 0x100>;
1047 reg = <0x0 0xff200000 0x0 0x10>;
1051 pinctrl-0 = <&pwm0_pin>;
1058 reg = <0x0 0xff200010 0x0 0x10>;
1062 pinctrl-0 = <&pwm1_pin>;
1069 reg = <0x0 0xff200020 0x0 0x10>;
1073 pinctrl-0 = <&pwm2_pin>;
1080 reg = <0x0 0xff200030 0x0 0x10>;
1084 pinctrl-0 = <&pwm3_pin>;
1091 reg = <0x0 0xff208000 0x0 0x10>;
1095 pinctrl-0 = <&pwm4_pin>;
1102 reg = <0x0 0xff208010 0x0 0x10>;
1106 pinctrl-0 = <&pwm5_pin>;
1113 reg = <0x0 0xff208020 0x0 0x10>;
1117 pinctrl-0 = <&pwm6_pin>;
1124 reg = <0x0 0xff208030 0x0 0x10>;
1128 pinctrl-0 = <&pwm7_pin>;
1135 reg = <0x0 0xff210000 0x0 0x1000>;
1149 reg = <0x0 0xff240000 0x0 0x4000>;
1161 reg = <0x0 0xff280000 0x0 0x100>;
1172 pinctrl-0 = <&tsadc_otp_pin>;
1181 reg = <0x0 0xff288000 0x0 0x100>;
1193 reg = <0x0 0xff290000 0x0 0x4000>;
1204 reg = <0x07 0x10>;
1207 reg = <0x17 0x1>;
1210 reg = <0x1e 0x1>;
1217 reg = <0x0 0xff2b0000 0x0 0x1000>;
1228 reg = <0x0 0xff2bc000 0x0 0x1000>;
1250 reg = <0x0 0xff2c0000 0x0 0x10000>;
1256 reg = <0x100 0x20>;
1259 #clock-cells = <0>;
1266 #phy-cells = <0>;
1273 #phy-cells = <0>;
1286 reg = <0x0 0xff2e0000 0x0 0x10000>,
1287 <0x0 0xff450000 0x0 0x10000>;
1294 #phy-cells = <0>;
1301 reg = <0x0 0xff2f0000 0x0 0x4000>;
1312 reg = <0x0 0xff300000 0x0 0x40000>;
1328 reg = <0x0 0xff340000 0x0 0x10000>;
1340 reg = <0x0 0xff350000 0x0 0x10000>;
1352 reg = <0x0 0xff360000 0x0 0x10000>;
1366 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
1375 reg = <0x0 0xff370000 0x0 0x4000>;
1381 fifo-depth = <0x100>;
1384 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1391 reg = <0x0 0xff380000 0x0 0x4000>;
1397 fifo-depth = <0x100>;
1400 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1407 reg = <0x0 0xff390000 0x0 0x4000>;
1413 fifo-depth = <0x100>;
1416 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1423 reg = <0x0 0xff3a0000 0x0 0x4000>;
1434 reg = <0x0 0xff3b0000 0x0 0x4000>;
1436 nandc_id = <0>;
1447 reg = <0x0 0xff400000 0x0 0x4000>;
1473 rockchip,low-temp = <0>;
1477 0 480 50000
1484 0 50000 0
1489 rockchip,pvtm-ch = <0 0>;
1529 0 69850 0
1535 rockchip,pvtm-ch = <0 0>;
1565 rockchip,grf-offset = <0x0410>;
1566 rockchip,grf-values = <0x80008000>, <0x80000000>, <0x80000000>;
1573 reg = <0x0 0xff442400 0x0 0x400>;
1583 rockchip,taskqueue-node = <0>;
1584 rockchip,resetgroup-node = <0>;
1590 reg = <0x0 0xff442800 0x0 0x100>;
1597 #iommu-cells = <0>;
1603 reg = <0x0 0xff442000 0x0 0x400>;
1613 rockchip,taskqueue-node = <0>;
1614 rockchip,resetgroup-node = <0>;
1620 reg = <0x0 0xff440000 0x0 0x400>;
1633 rockchip,taskqueue-node = <0>;
1634 rockchip,resetgroup-node = <0>;
1641 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>;
1648 #iommu-cells = <0>;
1654 reg = <0x0 0xff450000 0x0 0x10000>;
1665 #size-cells = <0>;
1670 #size-cells = <0>;
1672 port@0 {
1673 reg = <0>;
1675 #size-cells = <0>;
1677 dsi_in_vopb: endpoint@0 {
1678 reg = <0>;
1692 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>;
1707 #size-cells = <0>;
1709 vopb_out_dsi: endpoint@0 {
1710 reg = <0>;
1728 reg = <0x0 0xff460f00 0x0 0x100>;
1734 #iommu-cells = <0>;
1741 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>;
1756 #size-cells = <0>;
1758 vopl_out_dsi: endpoint@0 {
1759 reg = <0>;
1777 reg = <0x0 0xff470f00 0x0 0x100>;
1783 #iommu-cells = <0>;
1791 reg = <0x0 0xff480000 0x0 0x1000>;
1801 reg = <0x0 0xff490000 0x0 0x200>;
1809 pinctrl-0 = <&dvp_d2d9_m0>;
1816 reg = <0x0 0xff490000 0x0 0x200>;
1829 reg = <0x0 0xff490800 0x0 0x100>;
1836 #iommu-cells = <0>;
1842 reg = <0x0 0xff4a0000 0x0 0x8000>;
1852 pinctrl-0 = <&cif_clkout_m0>;
1857 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>;
1867 reg = <0x0 0xff4a0000 0x0 0x8000>;
1885 reg = <0x0 0xff4a8000 0x0 0x100>;
1892 #iommu-cells = <0>;
1898 reg = <0x0 0xff518000 0x0 0x20>;
1903 reg = <0x0 0xff520000 0x0 0x20>;
1908 reg = <0x0 0xff52c000 0x0 0x20>;
1913 reg = <0x0 0xff538000 0x0 0x20>;
1918 reg = <0x0 0xff538080 0x0 0x20>;
1923 reg = <0x0 0xff538100 0x0 0x20>;
1928 reg = <0x0 0xff538180 0x0 0x20>;
1933 reg = <0x0 0xff540000 0x0 0x20>;
1938 reg = <0x0 0xff540080 0x0 0x20>;
1943 reg = <0x0 0xff548000 0x0 0x20>;
1948 reg = <0x0 0xff548080 0x0 0x20>;
1953 reg = <0x0 0xff548100 0x0 0x20>;
1958 reg = <0x0 0xff548180 0x0 0x20>;
1963 reg = <0x0 0xff548200 0x0 0x20>;
1968 reg = <0x0 0xff550000 0x0 0x20>;
1973 reg = <0x0 0xff550080 0x0 0x20>;
1978 reg = <0x0 0xff550100 0x0 0x20>;
1983 reg = <0x0 0xff550180 0x0 0x20>;
1988 reg = <0x0 0xff558000 0x0 0x20>;
1993 reg = <0x0 0xff558080 0x0 0x20>;
1997 reg = <0x00 0xff610000 0x00 0x400>;
2041 debug_print_level = <0>;
2059 0 50000 0
2064 rockchip,pvtm-ch = <0 0>;
2177 reg = <0x0 0xff040000 0x0 0x100>;
2189 reg = <0x0 0xff250000 0x0 0x100>;
2201 reg = <0x0 0xff260000 0x0 0x100>;
2213 reg = <0x0 0xff270000 0x0 0x100>;
2305 <0 RK_PB0 1 &pcfg_pull_none_smt>,
2306 <0 RK_PB1 1 &pcfg_pull_none_smt>;
2313 <0 RK_PC2 1 &pcfg_pull_none_smt>,
2314 <0 RK_PC3 1 &pcfg_pull_none_smt>;
2337 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2342 <0 RK_PA6 1 &pcfg_pull_none>;
2349 <0 RK_PB2 1 &pcfg_pull_up>,
2350 <0 RK_PB3 1 &pcfg_pull_up>;
2355 <0 RK_PB4 1 &pcfg_pull_none>;
2360 <0 RK_PB5 1 &pcfg_pull_none>;
2406 <0 RK_PC0 2 &pcfg_pull_up>,
2407 <0 RK_PC1 2 &pcfg_pull_up>;
2412 <0 RK_PC2 2 &pcfg_pull_none>;
2417 <0 RK_PC3 2 &pcfg_pull_none>;
2770 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
2972 <0 RK_PB7 1 &pcfg_pull_none>;
2979 <0 RK_PC0 1 &pcfg_pull_none>;
2993 <0 RK_PC1 1 &pcfg_pull_none>;