Lines Matching +full:0 +full:xee020000
31 * The external audio clocks are configured as 0 Hz fixed frequency
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #clock-cells = <0>;
50 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
129 #size-cells = <0>;
157 a57_0: cpu@0 {
159 reg = <0x0>;
174 reg = <0x1>;
188 reg = <0x100>;
203 reg = <0x101>;
216 reg = <0x102>;
229 reg = <0x103>;
240 L2_CA57: cache-controller-0 {
257 CPU_SLEEP_0: cpu-sleep-0 {
259 arm,psci-suspend-param = <0x0010000>;
268 arm,psci-suspend-param = <0x0010000>;
279 #clock-cells = <0>;
281 clock-frequency = <0>;
286 #clock-cells = <0>;
288 clock-frequency = <0>;
294 #clock-cells = <0>;
295 clock-frequency = <0>;
322 #clock-cells = <0>;
323 clock-frequency = <0>;
336 reg = <0 0xe6020000 0 0x0c>;
346 reg = <0 0xe6050000 0 0x50>;
350 gpio-ranges = <&pfc 0 0 16>;
361 reg = <0 0xe6051000 0 0x50>;
365 gpio-ranges = <&pfc 0 32 29>;
376 reg = <0 0xe6052000 0 0x50>;
380 gpio-ranges = <&pfc 0 64 15>;
391 reg = <0 0xe6053000 0 0x50>;
395 gpio-ranges = <&pfc 0 96 16>;
406 reg = <0 0xe6054000 0 0x50>;
410 gpio-ranges = <&pfc 0 128 18>;
421 reg = <0 0xe6055000 0 0x50>;
425 gpio-ranges = <&pfc 0 160 26>;
436 reg = <0 0xe6055400 0 0x50>;
440 gpio-ranges = <&pfc 0 192 32>;
451 reg = <0 0xe6055800 0 0x50>;
455 gpio-ranges = <&pfc 0 224 4>;
465 reg = <0 0xe6060000 0 0x50c>;
471 reg = <0 0xe60f0000 0 0x1004>;
484 reg = <0 0xe6130000 0 0x1004>;
503 reg = <0 0xe6140000 0 0x1004>;
522 reg = <0 0xe6148000 0 0x1004>;
540 reg = <0 0xe6150000 0 0x1000>;
544 #power-domain-cells = <0>;
550 reg = <0 0xe6160000 0 0x0200>;
555 reg = <0 0xe6180000 0 0x0400>;
561 reg = <0 0xe6198000 0 0x100>,
562 <0 0xe61a0000 0 0x100>,
563 <0 0xe61a8000 0 0x100>;
577 reg = <0 0xe61c0000 0 0x200>;
578 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
591 #size-cells = <0>;
594 reg = <0 0xe6500000 0 0x40>;
599 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
600 <&dmac2 0x91>, <&dmac2 0x90>;
608 #size-cells = <0>;
611 reg = <0 0xe6508000 0 0x40>;
616 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
617 <&dmac2 0x93>, <&dmac2 0x92>;
625 #size-cells = <0>;
628 reg = <0 0xe6510000 0 0x40>;
633 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
634 <&dmac2 0x95>, <&dmac2 0x94>;
642 #size-cells = <0>;
645 reg = <0 0xe66d0000 0 0x40>;
650 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
658 #size-cells = <0>;
661 reg = <0 0xe66d8000 0 0x40>;
666 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
674 #size-cells = <0>;
677 reg = <0 0xe66e0000 0 0x40>;
682 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
690 #size-cells = <0>;
693 reg = <0 0xe66e8000 0 0x40>;
698 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
706 #size-cells = <0>;
710 reg = <0 0xe60b0000 0 0x425>;
715 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
724 reg = <0 0xe6540000 0 0x60>;
730 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
731 <&dmac2 0x31>, <&dmac2 0x30>;
742 reg = <0 0xe6550000 0 0x60>;
748 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
749 <&dmac2 0x33>, <&dmac2 0x32>;
760 reg = <0 0xe6560000 0 0x60>;
766 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
767 <&dmac2 0x35>, <&dmac2 0x34>;
778 reg = <0 0xe66a0000 0 0x60>;
784 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
795 reg = <0 0xe66b0000 0 0x60>;
801 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
811 reg = <0 0xe6590000 0 0x200>;
814 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
815 <&usb_dmac1 0>, <&usb_dmac1 1>;
828 reg = <0 0xe65a0000 0 0x100>;
842 reg = <0 0xe65b0000 0 0x100>;
856 reg = <0 0xe65ee000 0 0x90>;
862 #phy-cells = <0>;
869 reg = <0x0 0xe6601000 0 0x1000>;
878 reg = <0 0xe6700000 0 0x10000>;
907 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
920 reg = <0 0xe7300000 0 0x10000>;
949 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
962 reg = <0 0xe7310000 0 0x10000>;
1003 reg = <0 0xe6740000 0 0x1000>;
1004 renesas,ipmmu-main = <&ipmmu_mm 0>;
1011 reg = <0 0xe7740000 0 0x1000>;
1019 reg = <0 0xe6570000 0 0x1000>;
1027 reg = <0 0xff8b0000 0 0x1000>;
1035 reg = <0 0xe67b0000 0 0x1000>;
1044 reg = <0 0xec670000 0 0x1000>;
1052 reg = <0 0xfd800000 0 0x1000>;
1060 reg = <0 0xfd950000 0 0x1000>;
1068 reg = <0 0xffc80000 0 0x1000>;
1076 reg = <0 0xfe6b0000 0 0x1000>;
1084 reg = <0 0xfebd0000 0 0x1000>;
1093 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1132 #size-cells = <0>;
1139 reg = <0 0xe6c30000 0 0x1000>;
1155 reg = <0 0xe6c38000 0 0x1000>;
1171 reg = <0 0xe66c0000 0 0x8000>;
1195 reg = <0 0xe6e30000 0 8>;
1205 reg = <0 0xe6e31000 0 8>;
1215 reg = <0 0xe6e32000 0 8>;
1225 reg = <0 0xe6e33000 0 8>;
1235 reg = <0 0xe6e34000 0 8>;
1245 reg = <0 0xe6e35000 0 8>;
1255 reg = <0 0xe6e36000 0 8>;
1266 reg = <0 0xe6e60000 0 64>;
1272 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1273 <&dmac2 0x51>, <&dmac2 0x50>;
1283 reg = <0 0xe6e68000 0 64>;
1289 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1290 <&dmac2 0x53>, <&dmac2 0x52>;
1300 reg = <0 0xe6e88000 0 64>;
1306 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1307 <&dmac2 0x13>, <&dmac2 0x12>;
1317 reg = <0 0xe6c50000 0 64>;
1323 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1333 reg = <0 0xe6c40000 0 64>;
1339 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1349 reg = <0 0xe6f30000 0 64>;
1355 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1356 <&dmac2 0x5b>, <&dmac2 0x5a>;
1365 reg = <0 0xe6e80000 0 0x148>;
1377 reg = <0 0xe6e90000 0 0x0064>;
1380 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1381 <&dmac2 0x41>, <&dmac2 0x40>;
1386 #size-cells = <0>;
1393 reg = <0 0xe6ea0000 0 0x0064>;
1396 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1397 <&dmac2 0x43>, <&dmac2 0x42>;
1402 #size-cells = <0>;
1409 reg = <0 0xe6c00000 0 0x0064>;
1412 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1417 #size-cells = <0>;
1424 reg = <0 0xe6c10000 0 0x0064>;
1427 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1432 #size-cells = <0>;
1438 reg = <0 0xe6ef0000 0 0x1000>;
1443 renesas,id = <0>;
1448 #size-cells = <0>;
1452 #size-cells = <0>;
1456 vin0csi20: endpoint@0 {
1457 reg = <0>;
1470 reg = <0 0xe6ef1000 0 0x1000>;
1480 #size-cells = <0>;
1484 #size-cells = <0>;
1488 vin1csi20: endpoint@0 {
1489 reg = <0>;
1502 reg = <0 0xe6ef2000 0 0x1000>;
1512 #size-cells = <0>;
1516 #size-cells = <0>;
1520 vin2csi20: endpoint@0 {
1521 reg = <0>;
1534 reg = <0 0xe6ef3000 0 0x1000>;
1544 #size-cells = <0>;
1548 #size-cells = <0>;
1552 vin3csi20: endpoint@0 {
1553 reg = <0>;
1566 reg = <0 0xe6ef4000 0 0x1000>;
1576 #size-cells = <0>;
1580 #size-cells = <0>;
1584 vin4csi20: endpoint@0 {
1585 reg = <0>;
1598 reg = <0 0xe6ef5000 0 0x1000>;
1608 #size-cells = <0>;
1612 #size-cells = <0>;
1616 vin5csi20: endpoint@0 {
1617 reg = <0>;
1630 reg = <0 0xe6ef6000 0 0x1000>;
1640 #size-cells = <0>;
1644 #size-cells = <0>;
1648 vin6csi20: endpoint@0 {
1649 reg = <0>;
1662 reg = <0 0xe6ef7000 0 0x1000>;
1672 #size-cells = <0>;
1676 #size-cells = <0>;
1680 vin7csi20: endpoint@0 {
1681 reg = <0>;
1695 reg = <0 0xe6f40000 0 0x64>;
1699 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1710 reg = <0 0xe6f50000 0 0x64>;
1714 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1725 reg = <0 0xe6f60000 0 0x64>;
1729 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1740 reg = <0 0xe6f70000 0 0x64>;
1744 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1755 reg = <0 0xe6f80000 0 0x64>;
1759 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1770 reg = <0 0xe6f90000 0 0x64>;
1774 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1785 reg = <0 0xe6fa0000 0 0x64>;
1789 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1800 reg = <0 0xe6fb0000 0 0x64>;
1804 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1816 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1822 * clkout : #clock-cells = <0>; <&rcar_sound>;
1826 reg = <0 0xec500000 0 0x1000>, /* SCU */
1827 <0 0xec5a0000 0 0x100>, /* ADG */
1828 <0 0xec540000 0 0x1000>, /* SSIU */
1829 <0 0xec541000 0 0x280>, /* SSI */
1830 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1853 "ssi.1", "ssi.0",
1856 "src.1", "src.0",
1857 "mix.1", "mix.0",
1858 "ctu.1", "ctu.0",
1859 "dvc.0", "dvc.1",
1871 "ssi.1", "ssi.0";
1875 ctu00: ctu-0 { };
1886 dvc0: dvc-0 {
1887 dmas = <&audma1 0xbc>;
1891 dmas = <&audma1 0xbe>;
1897 mix0: mix-0 { };
1902 src0: src-0 {
1904 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1909 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1914 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1919 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1924 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1929 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1934 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1939 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1944 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1949 dmas = <&audma0 0x97>, <&audma1 0xba>;
1955 ssi0: ssi-0 {
1957 dmas = <&audma0 0x01>, <&audma1 0x02>;
1962 dmas = <&audma0 0x03>, <&audma1 0x04>;
1967 dmas = <&audma0 0x05>, <&audma1 0x06>;
1972 dmas = <&audma0 0x07>, <&audma1 0x08>;
1977 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1982 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1987 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1992 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1997 dmas = <&audma0 0x11>, <&audma1 0x12>;
2002 dmas = <&audma0 0x13>, <&audma1 0x14>;
2008 ssiu00: ssiu-0 {
2009 dmas = <&audma0 0x15>, <&audma1 0x16>;
2013 dmas = <&audma0 0x35>, <&audma1 0x36>;
2017 dmas = <&audma0 0x37>, <&audma1 0x38>;
2021 dmas = <&audma0 0x47>, <&audma1 0x48>;
2025 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2029 dmas = <&audma0 0x43>, <&audma1 0x44>;
2033 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2037 dmas = <&audma0 0x53>, <&audma1 0x54>;
2041 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2045 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2049 dmas = <&audma0 0x57>, <&audma1 0x58>;
2053 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2057 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2061 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2065 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2069 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2073 dmas = <&audma0 0x63>, <&audma1 0x64>;
2077 dmas = <&audma0 0x67>, <&audma1 0x68>;
2081 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2085 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2089 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2093 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2097 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2101 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2105 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2109 dmas = <&audma0 0x21>, <&audma1 0x22>;
2113 dmas = <&audma0 0x23>, <&audma1 0x24>;
2117 dmas = <&audma0 0x25>, <&audma1 0x26>;
2121 dmas = <&audma0 0x27>, <&audma1 0x28>;
2125 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2129 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2133 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2137 dmas = <&audma0 0x71>, <&audma1 0x72>;
2141 dmas = <&audma0 0x17>, <&audma1 0x18>;
2145 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2149 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2153 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2157 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2161 dmas = <&audma0 0x31>, <&audma1 0x32>;
2165 dmas = <&audma0 0x33>, <&audma1 0x34>;
2169 dmas = <&audma0 0x73>, <&audma1 0x74>;
2173 dmas = <&audma0 0x75>, <&audma1 0x76>;
2177 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2181 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2185 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2189 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2193 dmas = <&audma0 0x81>, <&audma1 0x82>;
2197 dmas = <&audma0 0x83>, <&audma1 0x84>;
2201 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2205 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2209 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2213 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2222 reg = <0 0xec700000 0 0x10000>;
2251 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2264 reg = <0 0xec720000 0 0x10000>;
2306 reg = <0 0xee000000 0 0xc00>;
2317 reg = <0 0xee020000 0 0x400>;
2327 reg = <0 0xee080000 0 0x100>;
2339 reg = <0 0xee0a0000 0 0x100>;
2351 reg = <0 0xee080100 0 0x100>;
2364 reg = <0 0xee0a0100 0 0x100>;
2378 reg = <0 0xee080200 0 0x700>;
2390 reg = <0 0xee0a0200 0 0x700>;
2401 reg = <0 0xee100000 0 0x2000>;
2414 reg = <0 0xee120000 0 0x2000>;
2427 reg = <0 0xee140000 0 0x2000>;
2440 reg = <0 0xee160000 0 0x2000>;
2453 #address-cells = <0>;
2455 reg = <0x0 0xf1010000 0 0x1000>,
2456 <0x0 0xf1020000 0 0x20000>,
2457 <0x0 0xf1040000 0 0x20000>,
2458 <0x0 0xf1060000 0 0x20000>;
2470 reg = <0 0xfe000000 0 0x80000>;
2473 bus-range = <0x00 0xff>;
2475 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2476 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2477 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2478 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2480 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2485 interrupt-map-mask = <0 0 0 0>;
2486 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2497 reg = <0 0xee800000 0 0x80000>;
2500 bus-range = <0x00 0xff>;
2502 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2503 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2504 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2505 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2507 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2512 interrupt-map-mask = <0 0 0 0>;
2513 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2524 reg = <0 0xfe860000 0 0x2000>;
2534 reg = <0 0xfe870000 0 0x2000>;
2543 reg = <0 0xfe940000 0 0x2400>;
2553 reg = <0 0xfe950000 0 0x200>;
2561 reg = <0 0xfe96f000 0 0x200>;
2569 reg = <0 0xfe9af000 0 0x200>;
2578 reg = <0 0xfea27000 0 0x200>;
2587 reg = <0 0xfea2f000 0 0x200>;
2596 reg = <0 0xfea37000 0 0x200>;
2605 reg = <0 0xfe960000 0 0x8000>;
2616 reg = <0 0xfea20000 0 0x5000>;
2627 reg = <0 0xfea28000 0 0x5000>;
2638 reg = <0 0xfea30000 0 0x5000>;
2649 reg = <0 0xfe9a0000 0 0x8000>;
2661 reg = <0 0xfea40000 0 0x1000>;
2670 reg = <0 0xfea50000 0 0x1000>;
2679 reg = <0 0xfea60000 0 0x1000>;
2687 reg = <0 0xfea80000 0 0x10000>;
2696 #size-cells = <0>;
2700 #size-cells = <0>;
2704 csi20vin0: endpoint@0 {
2705 reg = <0>;
2742 reg = <0 0xfeaa0000 0 0x10000>;
2751 #size-cells = <0>;
2755 #size-cells = <0>;
2759 csi40vin0: endpoint@0 {
2760 reg = <0>;
2798 reg = <0 0xfead0000 0 0x10000>;
2808 #size-cells = <0>;
2809 port@0 {
2810 reg = <0>;
2827 reg = <0 0xfeb00000 0 0x70000>;
2833 clock-names = "du.0", "du.1", "du.2";
2835 reset-names = "du.0", "du.2";
2838 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2844 #size-cells = <0>;
2846 port@0 {
2847 reg = <0>;
2868 reg = <0 0xfeb90000 0 0x14>;
2876 #size-cells = <0>;
2878 port@0 {
2879 reg = <0>;
2894 reg = <0 0xfff00044 0 4>;
2902 thermal-sensors = <&tsc 0>;
2943 cooling-device = <&a53_0 0 2>;
2974 #clock-cells = <0>;
2975 clock-frequency = <0>;
2980 #clock-cells = <0>;
2981 clock-frequency = <0>;