Lines Matching +full:0 +full:xe6ef2000
32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
106 #size-cells = <0>;
134 a57_0: cpu@0 {
136 reg = <0x0>;
150 reg = <0x1>;
163 reg = <0x100>;
177 reg = <0x101>;
189 reg = <0x102>;
201 reg = <0x103>;
211 L2_CA57: cache-controller-0 {
228 #clock-cells = <0>;
230 clock-frequency = <0>;
235 #clock-cells = <0>;
237 clock-frequency = <0>;
243 #clock-cells = <0>;
244 clock-frequency = <0>;
271 #clock-cells = <0>;
272 clock-frequency = <0>;
285 reg = <0 0xe6020000 0 0x0c>;
295 reg = <0 0xe6050000 0 0x50>;
299 gpio-ranges = <&pfc 0 0 16>;
310 reg = <0 0xe6051000 0 0x50>;
314 gpio-ranges = <&pfc 0 32 29>;
325 reg = <0 0xe6052000 0 0x50>;
329 gpio-ranges = <&pfc 0 64 15>;
340 reg = <0 0xe6053000 0 0x50>;
344 gpio-ranges = <&pfc 0 96 16>;
355 reg = <0 0xe6054000 0 0x50>;
359 gpio-ranges = <&pfc 0 128 18>;
370 reg = <0 0xe6055000 0 0x50>;
374 gpio-ranges = <&pfc 0 160 26>;
385 reg = <0 0xe6055400 0 0x50>;
389 gpio-ranges = <&pfc 0 192 32>;
400 reg = <0 0xe6055800 0 0x50>;
404 gpio-ranges = <&pfc 0 224 4>;
414 reg = <0 0xe6060000 0 0x50c>;
420 reg = <0 0xe60f0000 0 0x1004>;
433 reg = <0 0xe6130000 0 0x1004>;
452 reg = <0 0xe6140000 0 0x1004>;
471 reg = <0 0xe6148000 0 0x1004>;
489 reg = <0 0xe6150000 0 0x0bb0>;
493 #power-domain-cells = <0>;
499 reg = <0 0xe6160000 0 0x018c>;
504 reg = <0 0xe6180000 0 0x0400>;
510 reg = <0 0xe6198000 0 0x100>,
511 <0 0xe61a0000 0 0x100>,
512 <0 0xe61a8000 0 0x100>;
526 reg = <0 0xe61c0000 0 0x200>;
527 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
540 reg = <0 0xe61e0000 0 0x30>;
553 reg = <0 0xe6fc0000 0 0x30>;
566 reg = <0 0xe6fd0000 0 0x30>;
579 reg = <0 0xe6fe0000 0 0x30>;
592 reg = <0 0xffc00000 0 0x30>;
605 #size-cells = <0>;
608 reg = <0 0xe6500000 0 0x40>;
613 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
614 <&dmac2 0x91>, <&dmac2 0x90>;
622 #size-cells = <0>;
625 reg = <0 0xe6508000 0 0x40>;
630 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
631 <&dmac2 0x93>, <&dmac2 0x92>;
639 #size-cells = <0>;
642 reg = <0 0xe6510000 0 0x40>;
647 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
648 <&dmac2 0x95>, <&dmac2 0x94>;
656 #size-cells = <0>;
659 reg = <0 0xe66d0000 0 0x40>;
664 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
672 #size-cells = <0>;
675 reg = <0 0xe66d8000 0 0x40>;
680 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
688 #size-cells = <0>;
691 reg = <0 0xe66e0000 0 0x40>;
696 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
704 #size-cells = <0>;
707 reg = <0 0xe66e8000 0 0x40>;
712 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
720 #size-cells = <0>;
724 reg = <0 0xe60b0000 0 0x425>;
729 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
738 reg = <0 0xe6540000 0 0x60>;
744 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
745 <&dmac2 0x31>, <&dmac2 0x30>;
756 reg = <0 0xe6550000 0 0x60>;
762 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
763 <&dmac2 0x33>, <&dmac2 0x32>;
774 reg = <0 0xe6560000 0 0x60>;
780 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
781 <&dmac2 0x35>, <&dmac2 0x34>;
792 reg = <0 0xe66a0000 0 0x60>;
798 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
809 reg = <0 0xe66b0000 0 0x60>;
815 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
825 reg = <0 0xe6590000 0 0x200>;
828 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
829 <&usb_dmac1 0>, <&usb_dmac1 1>;
842 reg = <0 0xe6590630 0 0x02>;
847 #clock-cells = <0>;
857 reg = <0 0xe65a0000 0 0x100>;
871 reg = <0 0xe65b0000 0 0x100>;
885 reg = <0 0xe65ee000 0 0x90>;
891 #phy-cells = <0>;
898 reg = <0 0xe6700000 0 0x10000>;
927 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
940 reg = <0 0xe7300000 0 0x10000>;
969 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
982 reg = <0 0xe7310000 0 0x10000>;
1023 reg = <0 0xe6740000 0 0x1000>;
1024 renesas,ipmmu-main = <&ipmmu_mm 0>;
1031 reg = <0 0xe7740000 0 0x1000>;
1039 reg = <0 0xe6570000 0 0x1000>;
1047 reg = <0 0xe67b0000 0 0x1000>;
1056 reg = <0 0xec670000 0 0x1000>;
1064 reg = <0 0xfd800000 0 0x1000>;
1072 reg = <0 0xfd950000 0 0x1000>;
1080 reg = <0 0xfe6b0000 0 0x1000>;
1088 reg = <0 0xfebd0000 0 0x1000>;
1097 reg = <0 0xe6800000 0 0x800>;
1134 rx-internal-delay-ps = <0>;
1135 tx-internal-delay-ps = <0>;
1138 #size-cells = <0>;
1145 reg = <0 0xe6c30000 0 0x1000>;
1161 reg = <0 0xe6c38000 0 0x1000>;
1177 reg = <0 0xe66c0000 0 0x8000>;
1201 reg = <0 0xe6e30000 0 0x8>;
1211 reg = <0 0xe6e31000 0 0x8>;
1221 reg = <0 0xe6e32000 0 0x8>;
1231 reg = <0 0xe6e33000 0 0x8>;
1241 reg = <0 0xe6e34000 0 0x8>;
1251 reg = <0 0xe6e35000 0 0x8>;
1261 reg = <0 0xe6e36000 0 0x8>;
1272 reg = <0 0xe6e60000 0 0x40>;
1278 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1279 <&dmac2 0x51>, <&dmac2 0x50>;
1289 reg = <0 0xe6e68000 0 0x40>;
1295 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1296 <&dmac2 0x53>, <&dmac2 0x52>;
1306 reg = <0 0xe6e88000 0 0x40>;
1312 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1313 <&dmac2 0x13>, <&dmac2 0x12>;
1323 reg = <0 0xe6c50000 0 0x40>;
1329 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1339 reg = <0 0xe6c40000 0 0x40>;
1345 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1355 reg = <0 0xe6f30000 0 0x40>;
1361 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1362 <&dmac2 0x5b>, <&dmac2 0x5a>;
1372 reg = <0 0xe6e90000 0 0x0064>;
1375 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1376 <&dmac2 0x41>, <&dmac2 0x40>;
1381 #size-cells = <0>;
1388 reg = <0 0xe6ea0000 0 0x0064>;
1391 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1392 <&dmac2 0x43>, <&dmac2 0x42>;
1397 #size-cells = <0>;
1404 reg = <0 0xe6c00000 0 0x0064>;
1407 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1412 #size-cells = <0>;
1419 reg = <0 0xe6c10000 0 0x0064>;
1422 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1427 #size-cells = <0>;
1433 reg = <0 0xe6ef0000 0 0x1000>;
1438 renesas,id = <0>;
1443 #size-cells = <0>;
1447 #size-cells = <0>;
1451 vin0csi20: endpoint@0 {
1452 reg = <0>;
1465 reg = <0 0xe6ef1000 0 0x1000>;
1475 #size-cells = <0>;
1479 #size-cells = <0>;
1483 vin1csi20: endpoint@0 {
1484 reg = <0>;
1497 reg = <0 0xe6ef2000 0 0x1000>;
1507 #size-cells = <0>;
1511 #size-cells = <0>;
1515 vin2csi20: endpoint@0 {
1516 reg = <0>;
1529 reg = <0 0xe6ef3000 0 0x1000>;
1539 #size-cells = <0>;
1543 #size-cells = <0>;
1547 vin3csi20: endpoint@0 {
1548 reg = <0>;
1561 reg = <0 0xe6ef4000 0 0x1000>;
1571 #size-cells = <0>;
1575 #size-cells = <0>;
1579 vin4csi20: endpoint@0 {
1580 reg = <0>;
1593 reg = <0 0xe6ef5000 0 0x1000>;
1603 #size-cells = <0>;
1607 #size-cells = <0>;
1611 vin5csi20: endpoint@0 {
1612 reg = <0>;
1625 reg = <0 0xe6ef6000 0 0x1000>;
1635 #size-cells = <0>;
1639 #size-cells = <0>;
1643 vin6csi20: endpoint@0 {
1644 reg = <0>;
1657 reg = <0 0xe6ef7000 0 0x1000>;
1667 #size-cells = <0>;
1671 #size-cells = <0>;
1675 vin7csi20: endpoint@0 {
1676 reg = <0>;
1691 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1697 * clkout : #clock-cells = <0>; <&rcar_sound>;
1701 reg = <0 0xec500000 0 0x1000>, /* SCU */
1702 <0 0xec5a0000 0 0x100>, /* ADG */
1703 <0 0xec540000 0 0x1000>, /* SSIU */
1704 <0 0xec541000 0 0x280>, /* SSI */
1705 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1728 "ssi.1", "ssi.0",
1731 "src.1", "src.0",
1732 "mix.1", "mix.0",
1733 "ctu.1", "ctu.0",
1734 "dvc.0", "dvc.1",
1746 "ssi.1", "ssi.0";
1750 ctu00: ctu-0 { };
1761 dvc0: dvc-0 {
1762 dmas = <&audma1 0xbc>;
1766 dmas = <&audma1 0xbe>;
1772 mix0: mix-0 { };
1777 src0: src-0 {
1779 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1784 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1789 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1794 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1799 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1804 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1809 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1814 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1819 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1824 dmas = <&audma0 0x97>, <&audma1 0xba>;
1830 ssi0: ssi-0 {
1832 dmas = <&audma0 0x01>, <&audma1 0x02>;
1837 dmas = <&audma0 0x03>, <&audma1 0x04>;
1842 dmas = <&audma0 0x05>, <&audma1 0x06>;
1847 dmas = <&audma0 0x07>, <&audma1 0x08>;
1852 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1857 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1862 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1867 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1872 dmas = <&audma0 0x11>, <&audma1 0x12>;
1877 dmas = <&audma0 0x13>, <&audma1 0x14>;
1883 ssiu00: ssiu-0 {
1884 dmas = <&audma0 0x15>, <&audma1 0x16>;
1888 dmas = <&audma0 0x35>, <&audma1 0x36>;
1892 dmas = <&audma0 0x37>, <&audma1 0x38>;
1896 dmas = <&audma0 0x47>, <&audma1 0x48>;
1900 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1904 dmas = <&audma0 0x43>, <&audma1 0x44>;
1908 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1912 dmas = <&audma0 0x53>, <&audma1 0x54>;
1916 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1920 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1924 dmas = <&audma0 0x57>, <&audma1 0x58>;
1928 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1932 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1936 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1940 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1944 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1948 dmas = <&audma0 0x63>, <&audma1 0x64>;
1952 dmas = <&audma0 0x67>, <&audma1 0x68>;
1956 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1960 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1964 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1968 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1972 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1976 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1980 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1984 dmas = <&audma0 0x21>, <&audma1 0x22>;
1988 dmas = <&audma0 0x23>, <&audma1 0x24>;
1992 dmas = <&audma0 0x25>, <&audma1 0x26>;
1996 dmas = <&audma0 0x27>, <&audma1 0x28>;
2000 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2004 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2008 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2012 dmas = <&audma0 0x71>, <&audma1 0x72>;
2016 dmas = <&audma0 0x17>, <&audma1 0x18>;
2020 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2024 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2028 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2032 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2036 dmas = <&audma0 0x31>, <&audma1 0x32>;
2040 dmas = <&audma0 0x33>, <&audma1 0x34>;
2044 dmas = <&audma0 0x73>, <&audma1 0x74>;
2048 dmas = <&audma0 0x75>, <&audma1 0x76>;
2052 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2056 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2060 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2064 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2068 dmas = <&audma0 0x81>, <&audma1 0x82>;
2072 dmas = <&audma0 0x83>, <&audma1 0x84>;
2076 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2080 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2084 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2088 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2097 reg = <0 0xec700000 0 0x10000>;
2126 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2139 reg = <0 0xec720000 0 0x10000>;
2181 reg = <0 0xee000000 0 0xc00>;
2192 reg = <0 0xee020000 0 0x400>;
2202 reg = <0 0xee080000 0 0x100>;
2214 reg = <0 0xee0a0000 0 0x100>;
2226 reg = <0 0xee080100 0 0x100>;
2239 reg = <0 0xee0a0100 0 0x100>;
2253 reg = <0 0xee080200 0 0x700>;
2265 reg = <0 0xee0a0200 0 0x700>;
2276 reg = <0 0xee100000 0 0x2000>;
2288 reg = <0 0xee120000 0 0x2000>;
2300 reg = <0 0xee140000 0 0x2000>;
2312 reg = <0 0xee160000 0 0x2000>;
2324 #address-cells = <0>;
2326 reg = <0x0 0xf1010000 0 0x1000>,
2327 <0x0 0xf1020000 0 0x20000>,
2328 <0x0 0xf1040000 0 0x20000>,
2329 <0x0 0xf1060000 0 0x20000>;
2341 reg = <0 0xfe000000 0 0x80000>;
2344 bus-range = <0x00 0xff>;
2346 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2347 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2348 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2349 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2351 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2356 interrupt-map-mask = <0 0 0 0>;
2357 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2368 reg = <0 0xee800000 0 0x80000>;
2371 bus-range = <0x00 0xff>;
2373 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2374 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2375 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2376 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2378 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2383 interrupt-map-mask = <0 0 0 0>;
2384 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2395 reg = <0x0 0xfe000000 0 0x80000>,
2396 <0x0 0xfe100000 0 0x100000>,
2397 <0x0 0xfe200000 0 0x200000>,
2398 <0x0 0x30000000 0 0x8000000>,
2399 <0x0 0x38000000 0 0x8000000>;
2414 reg = <0x0 0xee800000 0 0x80000>,
2415 <0x0 0xee900000 0 0x100000>,
2416 <0x0 0xeea00000 0 0x200000>,
2417 <0x0 0xc0000000 0 0x8000000>,
2418 <0x0 0xc8000000 0 0x8000000>;
2432 reg = <0 0xfe940000 0 0x2400>;
2442 reg = <0 0xfe950000 0 0x200>;
2450 reg = <0 0xfe96f000 0 0x200>;
2458 reg = <0 0xfea27000 0 0x200>;
2467 reg = <0 0xfea2f000 0 0x200>;
2476 reg = <0 0xfea37000 0 0x200>;
2485 reg = <0 0xfe9af000 0 0x200>;
2494 reg = <0 0xfe960000 0 0x8000>;
2505 reg = <0 0xfea20000 0 0x5000>;
2516 reg = <0 0xfea28000 0 0x5000>;
2527 reg = <0 0xfea30000 0 0x5000>;
2538 reg = <0 0xfe9a0000 0 0x8000>;
2549 reg = <0 0xfea80000 0 0x10000>;
2558 #size-cells = <0>;
2562 #size-cells = <0>;
2566 csi20vin0: endpoint@0 {
2567 reg = <0>;
2604 reg = <0 0xfeaa0000 0 0x10000>;
2613 #size-cells = <0>;
2617 #size-cells = <0>;
2621 csi40vin0: endpoint@0 {
2622 reg = <0>;
2661 reg = <0 0xfead0000 0 0x10000>;
2672 #size-cells = <0>;
2673 port@0 {
2674 reg = <0>;
2691 reg = <0 0xfeb00000 0 0x70000>;
2697 clock-names = "du.0", "du.1", "du.2";
2699 reset-names = "du.0", "du.2";
2702 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2706 #size-cells = <0>;
2708 port@0 {
2709 reg = <0>;
2730 reg = <0 0xfeb90000 0 0x14>;
2738 #size-cells = <0>;
2740 port@0 {
2741 reg = <0>;
2756 reg = <0 0xfff00044 0 4>;
2764 thermal-sensors = <&tsc 0>;
2800 cooling-device = <&a57_0 0 2>;
2805 cooling-device = <&a53_0 0 2>;
2836 #clock-cells = <0>;
2837 clock-frequency = <0>;
2842 #clock-cells = <0>;
2843 clock-frequency = <0>;