dts/qcom/sm8250.dtsi

152 			qcom,freq-domain = <&cpufreq_hw 1>;
166 			qcom,freq-domain = <&cpufreq_hw 1>;
181 			qcom,freq-domain = <&cpufreq_hw 1>;
207 			#reset-cells = <1>;
344 			#qcom,smem-state-cells = <1>;
368 			#qcom,smem-state-cells = <1>;
392 			#qcom,smem-state-cells = <1>;
412 			#clock-cells = <1>;
413 			#reset-cells = <1>;
414 			#power-domain-cells = <1>;
470 				#address-cells = <1>;
483 				#address-cells = <1>;
498 				#address-cells = <1>;
511 				#address-cells = <1>;
526 				#address-cells = <1>;
539 				#address-cells = <1>;
554 				#address-cells = <1>;
567 				#address-cells = <1>;
595 				#address-cells = <1>;
608 				#address-cells = <1>;
636 				#address-cells = <1>;
649 				#address-cells = <1>;
676 				#address-cells = <1>;
689 				#address-cells = <1>;
704 				#address-cells = <1>;
717 				#address-cells = <1>;
732 				#address-cells = <1>;
745 				#address-cells = <1>;
773 				#address-cells = <1>;
786 				#address-cells = <1>;
801 				#address-cells = <1>;
814 				#address-cells = <1>;
829 				#address-cells = <1>;
842 				#address-cells = <1>;
857 				#address-cells = <1>;
870 				#address-cells = <1>;
898 				#address-cells = <1>;
911 				#address-cells = <1>;
938 				#address-cells = <1>;
951 				#address-cells = <1>;
966 				#address-cells = <1>;
979 				#address-cells = <1>;
994 				#address-cells = <1>;
1007 				#address-cells = <1>;
1022 				#address-cells = <1>;
1035 				#address-cells = <1>;
1050 				#address-cells = <1>;
1063 				#address-cells = <1>;
1091 				#address-cells = <1>;
1104 				#address-cells = <1>;
1115 			#interconnect-cells = <1>;
1122 			#interconnect-cells = <1>;
1129 			#interconnect-cells = <1>;
1136 			#interconnect-cells = <1>;
1143 			#interconnect-cells = <1>;
1150 			#interconnect-cells = <1>;
1157 			#interconnect-cells = <1>;
1161 		ufs_mem_hc: ufshc@1d84000 {
1169 			#reset-cells = <1>;
1206 		ufs_mem_phy: phy@1d87000 {
1221 			ufs_mem_phy_lanes: lanes@1d87400 {
1231 		ipa_virt: interconnect@1e00000 {
1234 			#interconnect-cells = <1>;
1238 		tcsr_mutex: hwlock@1f40000 {
1241 			#hwlock-cells = <1>;
1358 			#clock-cells = <1>;
1359 			#reset-cells = <1>;
1360 			#power-domain-cells = <1>;
1392 					      <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1431 					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1466 			#interconnect-cells = <1>;
1473 			#interconnect-cells = <1>;
1480 			#interconnect-cells = <1>;
1488 					  <125 63 1>, <126 716 12>;
1502 			#thermal-sensor-cells = <1>;
1513 			#thermal-sensor-cells = <1>;
1526 			#power-domain-cells = <1>;
1538 			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2165 					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2230 				frame-number = <1>;
2236 			frame@17c25000 {
2278 			reg-names = "drv-0", "drv-1", "drv-2";
2285 					  <WAKE_TCS    3>, <CONTROL_TCS 1>;
2289 				#clock-cells = <1>;
2296 				#power-domain-cells = <1>;
2356 			#interconnect-cells = <1>;
2370 			#freq-domain-cells = <1>;
2391 			thermal-sensors = <&tsens0 1>;
3004 			thermal-sensors = <&tsens1 1>;