dts/qcom/sm8150.dtsi

111 			qcom,freq-domain = <&cpufreq_hw 1>;
125 			qcom,freq-domain = <&cpufreq_hw 1>;
139 			qcom,freq-domain = <&cpufreq_hw 1>;
165 			#reset-cells = <1>;
172 		#hwlock-cells = <1>;
232 			qcom,client-id = <1>;
321 			#qcom,smem-state-cells = <1>;
345 			#qcom,smem-state-cells = <1>;
365 		qcom,remote-pid = <1>;
369 			#qcom,smem-state-cells = <1>;
393 			#qcom,smem-state-cells = <1>;
414 			#clock-cells = <1>;
415 			#reset-cells = <1>;
416 			#power-domain-cells = <1>;
447 			#interconnect-cells = <1>;
454 			#interconnect-cells = <1>;
461 			#interconnect-cells = <1>;
468 			#interconnect-cells = <1>;
475 			#interconnect-cells = <1>;
482 			#interconnect-cells = <1>;
489 			#interconnect-cells = <1>;
493 		ufs_mem_hc: ufshc@1d84000 {
501 			#reset-cells = <1>;
536 		ufs_mem_phy: phy@1d87000 {
551 			ufs_mem_phy_lanes: lanes@1d87400 {
561 		ipa_virt: interconnect@1e00000 {
564 			#interconnect-cells = <1>;
568 		tcsr_mutex_regs: syscon@1f40000 {
579 					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
716 			#clock-cells = <1>;
717 			#reset-cells = <1>;
718 			#power-domain-cells = <1>;
725 			#global-interrupts = <1>;
764 					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
787 				qcom,remote-pid = <1>;
798 					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
845 			#clock-cells = <1>;
877 			#interconnect-cells = <1>;
884 			#interconnect-cells = <1>;
935 			#interconnect-cells = <1>;
946 			#power-domain-cells = <1>;
957 			#thermal-sensor-cells = <1>;
968 			#thermal-sensor-cells = <1>;
996 					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1036 			#mbox-cells = <1>;
1062 				frame-number = <1>;
1068 			frame@17c25000 {
1110 			reg-names = "drv-0", "drv-1", "drv-2";
1119 					  <CONTROL_TCS 1>;
1123 				#clock-cells = <1>;
1130 				#power-domain-cells = <1>;
1194 			#interconnect-cells = <1>;
1207 			#freq-domain-cells = <1>;
1213 		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
1224 			thermal-sensors = <&tsens0 1>;
1837 			thermal-sensors = <&tsens1 1>;