Lines Matching +full:0 +full:x01f40000
22 #clock-cells = <0>;
29 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x0 0x100>;
61 reg = <0x0 0x101>;
76 reg = <0x0 0x102>;
91 reg = <0x0 0x103>;
103 CPU4: cpu@0 {
106 reg = <0x0 0x0>;
125 reg = <0x0 0x1>;
140 reg = <0x0 0x2>;
155 reg = <0x0 0x3>;
208 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
211 arm,psci-suspend-param = <0x40000002>;
217 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
220 arm,psci-suspend-param = <0x40000003>;
227 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
230 arm,psci-suspend-param = <0x40000002>;
239 arm,psci-suspend-param = <0x40000003>;
246 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
249 arm,psci-suspend-param = <0x400000F2>;
256 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
259 arm,psci-suspend-param = <0x400000F3>;
266 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
269 arm,psci-suspend-param = <0x400000F4>;
276 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
279 arm,psci-suspend-param = <0x400000F2>;
289 arm,psci-suspend-param = <0x400000F3>;
299 arm,psci-suspend-param = <0x400000F4>;
317 reg = <0 0 0 0>;
336 reg = <0x0 0x85600000 0x0 0x100000>;
341 reg = <0x0 0x85700000 0x0 0x100000>;
346 reg = <0x0 0x85800000 0x0 0x600000>;
352 reg = <0x0 0x85e00000 0x0 0x200000>;
360 reg = <0 0x86000000 0 0x200000>;
365 reg = <0x0 0x86200000 0x0 0x3300000>;
370 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
375 reg = <0x0 0x92a00000 0x0 0x1e00000>;
380 reg = <0x0 0x94800000 0x0 0x200000>;
385 reg = <0x0 0x94a00000 0x0 0x100000>;
390 reg = <0x0 0x9f800000 0x0 0x800000>;
395 reg = <0x0 0xf6000000 0x0 0x800000>;
400 reg = <0x0 0xf6800000 0x0 0x1400000>;
406 reg = <0x0 0xfed00000 0x0 0xa00000>;
416 mboxes = <&apcs_glb 0>;
438 ranges = <0 0 0 0xffffffff>;
446 reg = <0x00100000 0x94000>;
455 reg = <0x00778000 0x7000>;
460 reg = <0x00780000 0x621c>;
467 reg = <0x00793000 0x1000>;
474 reg = <0x010ac000 0x4>;
479 reg = <0x016c0000 0x40000>;
522 reg = <0x01f40000 0x20000>;
527 reg = <0x03100000 0x400000>,
528 <0x03500000 0x400000>,
529 <0x03900000 0x400000>;
533 gpio-ranges = <&tlmm 0 0 114>;
801 reg = <0x05040000 0x10000>;
823 reg = <0x05100000 0x40000>;
854 reg = <0x0800f000 0x1000>,
855 <0x08400000 0x1000000>,
856 <0x09400000 0x1000000>,
857 <0x0a400000 0x220000>,
858 <0x0800a000 0x3000>;
862 qcom,ee = <0>;
863 qcom,channel = <0>;
865 #size-cells = <0>;
868 cell-index = <0>;
873 reg = <0x0c0c4000 0x1000>,
874 <0x0c0c5000 0x1000>;
887 pinctrl-0 = <&sdc1_state_on>;
898 reg = <0x0c144000 0x1f000>;
903 qcom,ee = <0>;
911 reg = <0x0c16f000 0x200>;
916 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
919 pinctrl-0 = <&blsp1_uart1_default>;
926 reg = <0x0c170000 0x1000>;
934 pinctrl-0 = <&blsp1_uart2_default>;
940 reg = <0x0c175000 0x600>;
949 pinctrl-0 = <&i2c1_default>;
952 #size-cells = <0>;
958 reg = <0x0c176000 0x600>;
967 pinctrl-0 = <&i2c2_default>;
970 #size-cells = <0>;
976 reg = <0x0c177000 0x600>;
985 pinctrl-0 = <&i2c3_default>;
988 #size-cells = <0>;
994 reg = <0x0c178000 0x600>;
1003 pinctrl-0 = <&i2c4_default>;
1006 #size-cells = <0>;
1012 reg = <0x0c184000 0x1f000>;
1017 qcom,ee = <0>;
1025 reg = <0x0c1af000 0x200>;
1030 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1033 pinctrl-0 = <&blsp2_uart1_default>;
1040 reg = <0x0c1b5000 0x600>;
1049 pinctrl-0 = <&i2c5_default>;
1052 #size-cells = <0>;
1058 reg = <0x0c1b6000 0x600>;
1067 pinctrl-0 = <&i2c6_default>;
1070 #size-cells = <0>;
1076 reg = <0x0c1b7000 0x600>;
1085 pinctrl-0 = <&i2c7_default>;
1088 #size-cells = <0>;
1094 reg = <0x0c1b8000 0x600>;
1103 pinctrl-0 = <&i2c8_default>;
1106 #size-cells = <0>;
1112 reg = <0x0cd00000 0x40000>;
1150 reg = <0x17911000 0x1000>;
1160 reg = <0x17920000 0x1000>;
1164 frame-number = <0>;
1165 interrupts = <0 8 0x4>,
1166 <0 7 0x4>;
1167 reg = <0x17921000 0x1000>,
1168 <0x17922000 0x1000>;
1173 interrupts = <0 9 0x4>;
1174 reg = <0x17923000 0x1000>;
1180 interrupts = <0 10 0x4>;
1181 reg = <0x17924000 0x1000>;
1187 interrupts = <0 11 0x4>;
1188 reg = <0x17925000 0x1000>;
1194 interrupts = <0 12 0x4>;
1195 reg = <0x17926000 0x1000>;
1201 interrupts = <0 13 0x4>;
1202 reg = <0x17927000 0x1000>;
1208 interrupts = <0 14 0x4>;
1209 reg = <0x17928000 0x1000>;
1216 reg = <0x17a00000 0x10000>, /* GICD */
1217 <0x17b00000 0x100000>; /* GICR * 8 */
1224 redistributor-stride = <0x0 0x20000>;
1231 syscon = <&tcsr_mutex_regs 0 0x1000>;
1237 interrupts = <GIC_PPI 1 0xf08>,
1238 <GIC_PPI 2 0xf08>,
1239 <GIC_PPI 3 0xf08>,
1240 <GIC_PPI 0 0xf08>;