Lines Matching +full:0 +full:x15080
60 #clock-cells = <0>;
66 #clock-cells = <0>;
76 reg = <0x0 0x80000000 0x0 0x600000>;
81 reg = <0x0 0x80600000 0x0 0x200000>;
86 reg = <0x0 0x80800000 0x0 0x20000>;
91 reg = <0x0 0x80820000 0x0 0x20000>;
97 reg = <0x0 0x808ff000 0x0 0x1000>;
102 reg = <0x0 0x80900000 0x0 0x200000>;
107 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 reg = <0x0 0x84400000 0x0 0x200000>;
123 #size-cells = <0>;
125 CPU0: cpu@0 {
128 reg = <0x0 0x0>;
140 qcom,freq-domain = <&cpufreq_hw 0>;
153 reg = <0x0 0x100>;
165 qcom,freq-domain = <&cpufreq_hw 0>;
175 reg = <0x0 0x200>;
187 qcom,freq-domain = <&cpufreq_hw 0>;
197 reg = <0x0 0x300>;
209 qcom,freq-domain = <&cpufreq_hw 0>;
219 reg = <0x0 0x400>;
231 qcom,freq-domain = <&cpufreq_hw 0>;
241 reg = <0x0 0x500>;
253 qcom,freq-domain = <&cpufreq_hw 0>;
263 reg = <0x0 0x600>;
285 reg = <0x0 0x700>;
343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
346 arm,psci-suspend-param = <0x40000003>;
353 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
356 arm,psci-suspend-param = <0x40000004>;
363 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
366 arm,psci-suspend-param = <0x40000003>;
376 arm,psci-suspend-param = <0x40000004>;
383 CLUSTER_SLEEP_0: cluster-sleep-0 {
386 arm,psci-suspend-param = <0x40003444>;
533 reg = <0 0x80000000 0 0>;
549 syscon = <&tcsr_mutex_regs 0 0x1000>;
567 qcom,local-pid = <0>;
591 qcom,local-pid = <0>;
612 qcom,local-pid = <0>;
643 soc: soc@0 {
646 ranges = <0 0 0 0 0x10 0>;
647 dma-ranges = <0 0 0 0 0x10 0>;
652 reg = <0 0x00100000 0 0x1f0000>;
664 reg = <0 0x00784000 0 0x8ff>,
665 <0 0x00780000 0 0x7a0>,
666 <0 0x00782000 0 0x100>,
667 <0 0x00786000 0 0x1fff>;
675 reg = <0x25b 0x1>;
682 reg = <0 0x7c4000 0 0x1000>,
683 <0 0x07c5000 0 0x1000>;
686 iommus = <&apps_smmu 0x60 0x0>;
694 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
695 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
751 reg = <0 0x008c0000 0 0x6000>;
758 iommus = <&apps_smmu 0x43 0x0>;
759 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
765 reg = <0 0x00880000 0 0x4000>;
769 pinctrl-0 = <&qup_i2c0_default>;
772 #size-cells = <0>;
773 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
774 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
775 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
783 reg = <0 0x00880000 0 0x4000>;
787 pinctrl-0 = <&qup_spi0_default>;
790 #size-cells = <0>;
793 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
794 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
801 reg = <0 0x00880000 0 0x4000>;
805 pinctrl-0 = <&qup_uart0_default>;
809 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
810 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
817 reg = <0 0x00884000 0 0x4000>;
821 pinctrl-0 = <&qup_i2c1_default>;
824 #size-cells = <0>;
825 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
826 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
827 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
835 reg = <0 0x00884000 0 0x4000>;
839 pinctrl-0 = <&qup_spi1_default>;
842 #size-cells = <0>;
845 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
846 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
853 reg = <0 0x00884000 0 0x4000>;
857 pinctrl-0 = <&qup_uart1_default>;
861 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
862 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
869 reg = <0 0x00888000 0 0x4000>;
873 pinctrl-0 = <&qup_i2c2_default>;
876 #size-cells = <0>;
877 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
879 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
887 reg = <0 0x00888000 0 0x4000>;
891 pinctrl-0 = <&qup_uart2_default>;
895 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
903 reg = <0 0x0088c000 0 0x4000>;
907 pinctrl-0 = <&qup_i2c3_default>;
910 #size-cells = <0>;
911 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
913 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
921 reg = <0 0x0088c000 0 0x4000>;
925 pinctrl-0 = <&qup_spi3_default>;
928 #size-cells = <0>;
931 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
932 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 reg = <0 0x0088c000 0 0x4000>;
943 pinctrl-0 = <&qup_uart3_default>;
947 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
948 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
955 reg = <0 0x00890000 0 0x4000>;
959 pinctrl-0 = <&qup_i2c4_default>;
962 #size-cells = <0>;
963 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
964 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
965 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
973 reg = <0 0x00890000 0 0x4000>;
977 pinctrl-0 = <&qup_uart4_default>;
981 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
989 reg = <0 0x00894000 0 0x4000>;
993 pinctrl-0 = <&qup_i2c5_default>;
996 #size-cells = <0>;
997 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
999 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1007 reg = <0 0x00894000 0 0x4000>;
1011 pinctrl-0 = <&qup_spi5_default>;
1014 #size-cells = <0>;
1017 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1018 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1025 reg = <0 0x00894000 0 0x4000>;
1029 pinctrl-0 = <&qup_uart5_default>;
1033 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1034 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1042 reg = <0 0x00ac0000 0 0x6000>;
1049 iommus = <&apps_smmu 0x4c3 0x0>;
1050 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
1056 reg = <0 0x00a80000 0 0x4000>;
1060 pinctrl-0 = <&qup_i2c6_default>;
1063 #size-cells = <0>;
1064 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1065 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1066 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1074 reg = <0 0x00a80000 0 0x4000>;
1078 pinctrl-0 = <&qup_spi6_default>;
1081 #size-cells = <0>;
1084 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1092 reg = <0 0x00a80000 0 0x4000>;
1096 pinctrl-0 = <&qup_uart6_default>;
1100 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1101 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1108 reg = <0 0x00a84000 0 0x4000>;
1112 pinctrl-0 = <&qup_i2c7_default>;
1115 #size-cells = <0>;
1116 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1117 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1118 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1126 reg = <0 0x00a84000 0 0x4000>;
1130 pinctrl-0 = <&qup_uart7_default>;
1134 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1142 reg = <0 0x00a88000 0 0x4000>;
1146 pinctrl-0 = <&qup_i2c8_default>;
1149 #size-cells = <0>;
1150 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1151 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1152 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1160 reg = <0 0x00a88000 0 0x4000>;
1164 pinctrl-0 = <&qup_spi8_default>;
1167 #size-cells = <0>;
1170 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1171 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1178 reg = <0 0x00a88000 0 0x4000>;
1182 pinctrl-0 = <&qup_uart8_default>;
1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1194 reg = <0 0x00a8c000 0 0x4000>;
1198 pinctrl-0 = <&qup_i2c9_default>;
1201 #size-cells = <0>;
1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1204 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1212 reg = <0 0x00a8c000 0 0x4000>;
1216 pinctrl-0 = <&qup_uart9_default>;
1220 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1228 reg = <0 0x00a90000 0 0x4000>;
1232 pinctrl-0 = <&qup_i2c10_default>;
1235 #size-cells = <0>;
1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1238 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1246 reg = <0 0x00a90000 0 0x4000>;
1250 pinctrl-0 = <&qup_spi10_default>;
1253 #size-cells = <0>;
1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1257 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1264 reg = <0 0x00a90000 0 0x4000>;
1268 pinctrl-0 = <&qup_uart10_default>;
1272 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1280 reg = <0 0x00a94000 0 0x4000>;
1284 pinctrl-0 = <&qup_i2c11_default>;
1287 #size-cells = <0>;
1288 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1290 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1298 reg = <0 0x00a94000 0 0x4000>;
1302 pinctrl-0 = <&qup_spi11_default>;
1305 #size-cells = <0>;
1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1309 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1316 reg = <0 0x00a94000 0 0x4000>;
1320 pinctrl-0 = <&qup_uart11_default>;
1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1333 reg = <0 0x01500000 0 0x28000>;
1340 reg = <0 0x01620000 0 0x17080>;
1347 reg = <0 0x01638000 0 0x1000>;
1354 reg = <0 0x01650000 0 0x1000>;
1361 reg = <0 0x016e0000 0 0x15080>;
1368 reg = <0 0x01705000 0 0x9000>;
1375 reg = <0 0x0170e000 0 0x6000>;
1382 reg = <0 0x01740000 0 0x1c100>;
1389 reg = <0 0x01e00000 0 0x1000>;
1397 iommus = <&apps_smmu 0x440 0x0>,
1398 <&apps_smmu 0x442 0x0>;
1399 reg = <0 0x1e40000 0 0x7000>,
1400 <0 0x1e47000 0 0x2000>,
1401 <0 0x1e04000 0 0x2c000>;
1406 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
1407 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
1408 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1418 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1419 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1420 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1425 qcom,smem-states = <&ipa_smp2p_out 0>,
1437 reg = <0 0x01f40000 0 0x40000>;
1442 reg = <0 0x01fc0000 0 0x40000>;
1447 reg = <0 0x03500000 0 0x300000>,
1448 <0 0x03900000 0 0x300000>,
1449 <0 0x03d00000 0 0x300000>;
1456 gpio-ranges = <&tlmm 0 0 120>;
1851 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1855 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1880 qcom,smem-states = <&modem_smp2p_out 0>;
1887 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1888 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
1903 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1904 <0 0x05061000 0 0x800>;
1907 iommus = <&adreno_smmu 0>;
1911 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
1963 reg = <0 0x05040000 0 0x10000>;
1986 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
1987 <0 0x0b490000 0 0x10000>;
2014 reg = <0 0x05090000 0 0x9000>;
2028 reg = <0 0x06002000 0 0x1000>,
2029 <0 0x16280000 0 0x180000>;
2046 reg = <0 0x06041000 0 0x1000>;
2061 #size-cells = <0>;
2074 reg = <0 0x06042000 0 0x1000>;
2089 #size-cells = <0>;
2102 reg = <0 0x06045000 0 0x1000>;
2117 #size-cells = <0>;
2119 port@0 {
2120 reg = <0>;
2137 reg = <0 0x06046000 0 0x1000>;
2161 reg = <0 0x06048000 0 0x1000>;
2162 iommus = <&apps_smmu 0x04a0 0x20>;
2179 reg = <0 0x06b04000 0 0x1000>;
2194 #size-cells = <0>;
2207 reg = <0 0x06b05000 0 0x1000>;
2231 reg = <0 0x06b06000 0 0x1000>;
2256 reg = <0 0x07040000 0 0x1000>;
2276 reg = <0 0x07140000 0 0x1000>;
2296 reg = <0 0x07240000 0 0x1000>;
2316 reg = <0 0x07340000 0 0x1000>;
2336 reg = <0 0x07440000 0 0x1000>;
2356 reg = <0 0x07540000 0 0x1000>;
2376 reg = <0 0x07640000 0 0x1000>;
2396 reg = <0 0x07740000 0 0x1000>;
2416 reg = <0 0x07800000 0 0x1000>;
2431 #size-cells = <0>;
2433 port@0 {
2434 reg = <0>;
2493 reg = <0 0x07810000 0 0x1000>;
2517 reg = <0 0x08804000 0 0x1000>;
2519 iommus = <&apps_smmu 0x80 0>;
2528 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2529 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2578 reg = <0 0x088dc000 0 0x600>;
2580 #size-cells = <0>;
2585 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2586 &config_noc SLAVE_QSPI_0 0>;
2595 reg = <0 0x088e3000 0 0x400>;
2597 #phy-cells = <0>;
2608 reg = <0 0x088e9000 0 0x18c>,
2609 <0 0x088e8000 0 0x38>;
2628 reg = <0 0x088e9200 0 0x128>,
2629 <0 0x088e9400 0 0x200>,
2630 <0 0x088e9c00 0 0x218>,
2631 <0 0x088e9600 0 0x128>,
2632 <0 0x088e9800 0 0x200>,
2633 <0 0x088e9a00 0 0x18>;
2634 #clock-cells = <0>;
2635 #phy-cells = <0>;
2644 reg = <0 0x09160000 0 0x03200>;
2651 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2658 reg = <0 0x09680000 0 0x3e200>;
2665 reg = <0 0x09990000 0 0x1600>;
2672 reg = <0 0x0a6f8800 0 0x400>;
2702 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2703 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2708 reg = <0 0x0a600000 0 0xe000>;
2710 iommus = <&apps_smmu 0x540 0>;
2721 reg = <0 0x0aa00000 0 0xff000>;
2735 iommus = <&apps_smmu 0x0c00 0x60>;
2737 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2738 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2781 reg = <0 0x0ab00000 0 0x10000>;
2791 reg = <0 0x0ac00000 0 0x1000>;
2798 reg = <0 0x0ae00000 0 0x1000>;
2815 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2818 iommus = <&apps_smmu 0x800 0x2>;
2828 reg = <0 0x0ae01000 0 0x8f000>,
2829 <0 0x0aeb0000 0 0x2008>;
2852 interrupts = <0>;
2858 #size-cells = <0>;
2860 port@0 {
2861 reg = <0>;
2896 reg = <0 0x0ae94000 0 0x400>;
2922 #size-cells = <0>;
2928 #size-cells = <0>;
2930 port@0 {
2931 reg = <0>;
2966 reg = <0 0x0ae94400 0 0x200>,
2967 <0 0x0ae94600 0 0x280>,
2968 <0 0x0ae94a00 0 0x1e0>;
2974 #phy-cells = <0>;
2986 reg = <0 0x0af00000 0 0x200000>;
2989 <&dsi_phy 0>,
2991 <0>,
2992 <0>;
3006 reg = <0 0x0b220000 0 0x30000>;
3007 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3015 reg = <0 0x0b2e0000 0 0x20000>;
3021 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3022 <0 0x0c222000 0 0x1ff>; /* SROT */
3032 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3033 <0 0x0c223000 0 0x1ff>; /* SROT */
3043 reg = <0 0x0c2a0000 0 0x31000>;
3049 reg = <0 0x0c300000 0 0x100000>;
3051 mboxes = <&apss_shared 0>;
3053 #clock-cells = <0>;
3059 reg = <0 0x0c440000 0 0x1100>,
3060 <0 0x0c600000 0 0x2000000>,
3061 <0 0x0e600000 0 0x100000>,
3062 <0 0x0e700000 0 0xa0000>,
3063 <0 0x0c40a000 0 0x26000>;
3067 qcom,ee = <0>;
3068 qcom,channel = <0>;
3073 cell-index = <0>;
3078 reg = <0 0x15000000 0 0x100000>;
3171 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3172 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3179 reg = <0 0x17a40000 0 0x20000>;
3186 reg = <0 0x17c00000 0 0x10000>;
3192 reg = <0 0x17c10000 0 0x1000>;
3201 reg = <0 0x17c20000 0 0x1000>;
3204 frame-number = <0>;
3207 reg = <0 0x17c21000 0 0x1000>,
3208 <0 0x17c22000 0 0x1000>;
3214 reg = <0 0x17c23000 0 0x1000>;
3221 reg = <0 0x17c25000 0 0x1000>;
3228 reg = <0 0x17c27000 0 0x1000>;
3235 reg = <0 0x17c29000 0 0x1000>;
3242 reg = <0 0x17c2b000 0 0x1000>;
3249 reg = <0 0x17c2d000 0 0x1000>;
3256 reg = <0 0x18200000 0 0x10000>,
3257 <0 0x18210000 0 0x10000>,
3258 <0 0x18220000 0 0x10000>;
3259 reg-names = "drv-0", "drv-1", "drv-2";
3263 qcom,tcs-offset = <0xd00>;
3338 reg = <0 0x18321000 0 0x1400>;
3348 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3359 reg = <0 0x18800000 0 0x800000>;
3361 iommus = <&apps_smmu 0xc0 0x1>;
3382 reg = <0 0x62d00000 0 0x50000>,
3383 <0 0x62780000 0 0x30000>;
3395 reg = <0 0x63000000 0 0x28>;
3406 polling-delay-passive = <0>;
3407 polling-delay = <0>;
3455 polling-delay-passive = <0>;
3456 polling-delay = <0>;
3504 polling-delay-passive = <0>;
3505 polling-delay = <0>;
3553 polling-delay-passive = <0>;
3554 polling-delay = <0>;
3602 polling-delay-passive = <0>;
3603 polling-delay = <0>;
3651 polling-delay-passive = <0>;
3652 polling-delay = <0>;
3700 polling-delay-passive = <0>;
3701 polling-delay = <0>;
3741 polling-delay-passive = <0>;
3742 polling-delay = <0>;
3782 polling-delay-passive = <0>;
3783 polling-delay = <0>;
3823 polling-delay-passive = <0>;
3824 polling-delay = <0>;
3864 polling-delay-passive = <0>;
3865 polling-delay = <0>;
3867 thermal-sensors = <&tsens0 0>;
3885 polling-delay-passive = <0>;
3886 polling-delay = <0>;
3905 polling-delay-passive = <0>;
3906 polling-delay = <0>;
3925 polling-delay-passive = <0>;
3926 polling-delay = <0>;
3946 polling-delay-passive = <0>;
3947 polling-delay = <0>;
3967 polling-delay-passive = <0>;
3968 polling-delay = <0>;
3970 thermal-sensors = <&tsens1 0>;
3988 polling-delay-passive = <0>;
3989 polling-delay = <0>;
4009 polling-delay-passive = <0>;
4010 polling-delay = <0>;
4030 polling-delay-passive = <0>;
4031 polling-delay = <0>;
4051 polling-delay-passive = <0>;
4052 polling-delay = <0>;
4072 polling-delay-passive = <0>;
4073 polling-delay = <0>;
4093 polling-delay-passive = <0>;
4094 polling-delay = <0>;
4114 polling-delay-passive = <0>;
4115 polling-delay = <0>;
4135 polling-delay-passive = <0>;
4136 polling-delay = <0>;
4156 polling-delay-passive = <0>;
4157 polling-delay = <0>;
4182 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;