Lines Matching +full:0 +full:x702d1000
21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
54 pinctrl-0 = <&pex_dpd_disable>;
59 pci@1,0 {
61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff>;
73 pci@2,0 {
75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff>;
90 reg = <0x0 0x50000000 0x0 0x00034000>;
102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
108 reg = <0x0 0x54040000 0x0 0x00040000>;
135 #size-cells = <0>;
141 reg = <0x0 0x54080000 0x0 0x700>;
153 ranges = <0x0 0x0 0x54080000 0x2000>;
157 reg = <0x838 0x1300>;
183 reg = <0x0 0x54100000 0x0 0x00040000>;
188 reg = <0x0 0x54200000 0x0 0x00040000>;
198 nvidia,head = <0>;
203 reg = <0x0 0x54240000 0x0 0x00040000>;
218 reg = <0x0 0x54300000 0x0 0x00040000>;
226 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
231 #size-cells = <0>;
236 reg = <0x0 0x54340000 0x0 0x00040000>;
249 reg = <0x0 0x54380000 0x0 0x00040000>;
255 reg = <0x0 0x54400000 0x0 0x00040000>;
263 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
268 #size-cells = <0>;
273 reg = <0x0 0x54480000 0x0 0x00040000>;
279 reg = <0x0 0x544c0000 0x0 0x00040000>;
285 reg = <0x0 0x54500000 0x0 0x00040000>;
291 reg = <0x0 0x54540000 0x0 0x00040000>;
301 pinctrl-0 = <&state_dpaux_aux>;
311 reg = <0x0 0x54580000 0x0 0x00040000>;
321 pinctrl-0 = <&state_dpaux1_aux>;
331 reg = <0x0 0x545c0000 0x0 0x00040000>;
358 #size-cells = <0>;
364 reg = <0x0 0x54600000 0x0 0x00040000>;
374 reg = <0x0 0x54680000 0x0 0x00040000>;
384 reg = <0x0 0x546c0000 0x0 0x00040000>;
395 #size-cells = <0>;
403 reg = <0x0 0x50041000 0x0 0x1000>,
404 <0x0 0x50042000 0x0 0x2000>,
405 <0x0 0x50044000 0x0 0x2000>,
406 <0x0 0x50046000 0x0 0x2000>;
414 reg = <0x0 0x57000000 0x0 0x01000000>,
415 <0x0 0x58000000 0x0 0x01000000>;
433 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
434 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
435 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
436 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
437 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
438 <0x0 0x60004500 0x0 0x40>; /* senary controller */
446 reg = <0x0 0x60005000 0x0 0x400>;
448 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
467 reg = <0x0 0x60006000 0x0 0x1000>;
474 reg = <0x0 0x60007000 0x0 0x1000>;
479 reg = <0x0 0x6000d000 0x0 0x1000>;
496 reg = <0x0 0x60020000 0x0 0x1400>;
538 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
539 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
544 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
545 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
549 nvidia,pull-down-strength = <0x8>;
550 nvidia,pull-up-strength = <0x8>;
556 nvidia,pull-down-strength = <0x4>;
557 nvidia,pull-up-strength = <0x3>;
563 nvidia,pull-down-strength = <0x10>;
564 nvidia,pull-up-strength = <0x10>;
570 nvidia,pull-down-strength = <0x8>;
571 nvidia,pull-up-strength = <0x8>;
577 nvidia,pull-down-strength = <0x4>;
578 nvidia,pull-up-strength = <0x3>;
584 nvidia,pull-down-strength = <0x10>;
585 nvidia,pull-up-strength = <0x10>;
600 reg = <0x0 0x70006000 0x0 0x40>;
614 reg = <0x0 0x70006040 0x0 0x40>;
628 reg = <0x0 0x70006200 0x0 0x40>;
642 reg = <0x0 0x70006300 0x0 0x40>;
656 reg = <0x0 0x7000a000 0x0 0x100>;
667 reg = <0x0 0x7000c000 0x0 0x100>;
670 #size-cells = <0>;
682 reg = <0x0 0x7000c400 0x0 0x100>;
685 #size-cells = <0>;
697 reg = <0x0 0x7000c500 0x0 0x100>;
700 #size-cells = <0>;
712 reg = <0x0 0x7000c700 0x0 0x100>;
715 #size-cells = <0>;
722 pinctrl-0 = <&state_dpaux1_i2c>;
730 reg = <0x0 0x7000d000 0x0 0x100>;
733 #size-cells = <0>;
745 reg = <0x0 0x7000d100 0x0 0x100>;
748 #size-cells = <0>;
755 pinctrl-0 = <&state_dpaux_i2c>;
763 reg = <0x0 0x7000d400 0x0 0x200>;
766 #size-cells = <0>;
778 reg = <0x0 0x7000d600 0x0 0x200>;
781 #size-cells = <0>;
793 reg = <0x0 0x7000d800 0x0 0x200>;
796 #size-cells = <0>;
808 reg = <0x0 0x7000da00 0x0 0x200>;
811 #size-cells = <0>;
823 reg = <0x0 0x7000e000 0x0 0x100>;
832 reg = <0x0 0x7000e400 0x0 0x400>;
844 #power-domain-cells = <0>;
865 #power-domain-cells = <0>;
871 #power-domain-cells = <0>;
877 #power-domain-cells = <0>;
883 #power-domain-cells = <0>;
891 #power-domain-cells = <0>;
900 #power-domain-cells = <0>;
941 reg = <0x0 0x7000f800 0x0 0x400>;
950 reg = <0x0 0x70019000 0x0 0x1000>;
962 reg = <0x0 0x7001b000 0x0 0x1000>,
963 <0x0 0x7001e000 0x0 0x1000>,
964 <0x0 0x7001f000 0x0 0x1000>;
974 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
975 <0x0 0x70020000 0x0 0x7000>, /* SATA */
976 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
990 reg = <0x0 0x70030000 0x0 0x10000>;
1006 reg = <0x0 0x70090000 0x0 0x8000>,
1007 <0x0 0x70098000 0x0 0x1000>,
1008 <0x0 0x70099000 0x0 0x1000>;
1043 reg = <0x0 0x7009f000 0x0 0x1000>;
1056 usb2-0 {
1058 #phy-cells = <0>;
1063 #phy-cells = <0>;
1068 #phy-cells = <0>;
1073 #phy-cells = <0>;
1084 hsic-0 {
1086 #phy-cells = <0>;
1091 #phy-cells = <0>;
1104 pcie-0 {
1106 #phy-cells = <0>;
1111 #phy-cells = <0>;
1116 #phy-cells = <0>;
1121 #phy-cells = <0>;
1126 #phy-cells = <0>;
1131 #phy-cells = <0>;
1136 #phy-cells = <0>;
1149 sata-0 {
1151 #phy-cells = <0>;
1158 usb2-0 {
1174 hsic-0 {
1178 usb3-0 {
1198 reg = <0x0 0x700b0000 0x0 0x200>;
1207 pinctrl-0 = <&sdmmc1_3v3>;
1211 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1212 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1213 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1214 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1215 nvidia,default-tap = <0x2>;
1216 nvidia,default-trim = <0x4>;
1227 reg = <0x0 0x700b0200 0x0 0x200>;
1235 pinctrl-0 = <&sdmmc2_1v8_drv>;
1236 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1237 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1238 nvidia,default-tap = <0x8>;
1239 nvidia,default-trim = <0x0>;
1245 reg = <0x0 0x700b0400 0x0 0x200>;
1254 pinctrl-0 = <&sdmmc3_3v3>;
1258 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1259 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1260 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1261 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1262 nvidia,default-tap = <0x3>;
1263 nvidia,default-trim = <0x3>;
1269 reg = <0x0 0x700b0600 0x0 0x200>;
1277 pinctrl-0 = <&sdmmc4_1v8_drv>;
1279 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1280 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1281 nvidia,default-tap = <0x8>;
1282 nvidia,default-trim = <0x0>;
1293 reg = <0x0 0x700d0000 0x0 0x8000>,
1294 <0x0 0x700d8000 0x0 0x1000>,
1295 <0x0 0x700d9000 0x0 0x1000>;
1312 reg = <0x0 0x700e3000 0x0 0x100>;
1321 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1322 <0 0x70110000 0 0x100>, /* I2C output control */
1323 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1324 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1332 #clock-cells = <0>;
1345 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1350 reg = <0x702e2000 0x2000>;
1384 reg = <0x702f9000 0x1000>,
1385 <0x702fa000 0x2000>;
1394 reg = <0x702d0800 0x800>;
1401 ranges = <0x702d0000 0x702d0000 0x0000e400>;
1406 reg = <0x702d0000 0x800>;
1432 reg = <0x702d1000 0x100>;
1445 reg = <0x702d1100 0x100>;
1458 reg = <0x702d1200 0x100>;
1471 reg = <0x702d1300 0x100>;
1484 reg = <0x702d1400 0x100>;
1497 reg = <0x702d4000 0x100>;
1509 reg = <0x702d4100 0x100>;
1521 reg = <0x702d4200 0x100>;
1535 reg = <0x0 0x70410000 0x0 0x1000>;
1538 #size-cells = <0>;
1550 reg = <0x0 0x7d000000 0x0 0x4000>;
1563 reg = <0x0 0x7d000000 0x0 0x4000>,
1564 <0x0 0x7d000000 0x0 0x4000>;
1572 nvidia,hssync-start-delay = <0>;
1577 nvidia,xcvr-lsfslew = <0>;
1588 reg = <0x0 0x7d004000 0x0 0x4000>;
1601 reg = <0x0 0x7d004000 0x0 0x4000>,
1602 <0x0 0x7d000000 0x0 0x4000>;
1610 nvidia,hssync-start-delay = <0>;
1615 nvidia,xcvr-lsfslew = <0>;
1625 #size-cells = <0>;
1627 cpu@0 {
1630 reg = <0>;
1670 arm,psci-suspend-param = <0x40000007>;
1691 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
1711 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1712 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1737 polling-delay = <0>;
1745 hysteresis = <0>;
1765 polling-delay-passive = <0>;
1766 polling-delay = <0>;
1786 hysteresis = <0>;
1793 cooling-device = <&emc 0 0>;
1806 polling-delay = <0>;
1814 hysteresis = <0>;
1834 polling-delay-passive = <0>;
1835 polling-delay = <0>;
1843 hysteresis = <0>;