Lines Matching full:bpmp

9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
54 			clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
55 				 <&bpmp TEGRA194_CLK_EQOS_AXI>,
56 				 <&bpmp TEGRA194_CLK_EQOS_RX>,
57 				 <&bpmp TEGRA194_CLK_EQOS_TX>,
58 				 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
60 			resets = <&bpmp TEGRA194_RESET_EQOS>;
77 			clocks = <&bpmp TEGRA194_CLK_APE>,
78 				 <&bpmp TEGRA194_CLK_APB2APE>;
80 			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
124 				clocks = <&bpmp TEGRA194_CLK_AHUB>;
139 				clocks = <&bpmp TEGRA194_CLK_APE>;
148 				clocks = <&bpmp TEGRA194_CLK_AHUB>;
150 				assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
151 				assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
208 					clocks = <&bpmp TEGRA194_CLK_I2S1>,
209 						 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
211 					assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
212 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
222 					clocks = <&bpmp TEGRA194_CLK_I2S2>,
223 						 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
225 					assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
226 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
236 					clocks = <&bpmp TEGRA194_CLK_I2S3>,
237 						 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
239 					assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
240 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
250 					clocks = <&bpmp TEGRA194_CLK_I2S4>,
251 						 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
253 					assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
254 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
264 					clocks = <&bpmp TEGRA194_CLK_I2S5>,
265 						 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
267 					assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
268 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
278 					clocks = <&bpmp TEGRA194_CLK_I2S6>,
279 						 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
281 					assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
282 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
292 					clocks = <&bpmp TEGRA194_CLK_DMIC1>;
294 					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
295 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
305 					clocks = <&bpmp TEGRA194_CLK_DMIC2>;
307 					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
308 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
318 					clocks = <&bpmp TEGRA194_CLK_DMIC3>;
320 					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
321 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
331 					clocks = <&bpmp TEGRA194_CLK_DMIC4>;
333 					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
334 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
344 					clocks = <&bpmp TEGRA194_CLK_DSPK1>;
346 					assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
347 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
357 					clocks = <&bpmp TEGRA194_CLK_DSPK2>;
359 					assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
360 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
437 				clocks = <&bpmp TEGRA194_CLK_EMC>;
442 				nvidia,bpmp = <&bpmp>;
451 			clocks = <&bpmp TEGRA194_CLK_UARTA>;
453 			resets = <&bpmp TEGRA194_RESET_UARTA>;
463 			clocks = <&bpmp TEGRA194_CLK_UARTB>;
465 			resets = <&bpmp TEGRA194_RESET_UARTB>;
475 			clocks = <&bpmp TEGRA194_CLK_UARTD>;
477 			resets = <&bpmp TEGRA194_RESET_UARTD>;
487 			clocks = <&bpmp TEGRA194_CLK_UARTE>;
489 			resets = <&bpmp TEGRA194_RESET_UARTE>;
499 			clocks = <&bpmp TEGRA194_CLK_UARTF>;
501 			resets = <&bpmp TEGRA194_RESET_UARTF>;
512 			clocks = <&bpmp TEGRA194_CLK_I2C1>;
514 			resets = <&bpmp TEGRA194_RESET_I2C1>;
524 			clocks = <&bpmp TEGRA194_CLK_UARTH>;
526 			resets = <&bpmp TEGRA194_RESET_UARTH>;
537 			clocks = <&bpmp TEGRA194_CLK_I2C3>;
539 			resets = <&bpmp TEGRA194_RESET_I2C3>;
551 			clocks = <&bpmp TEGRA194_CLK_I2C4>;
553 			resets = <&bpmp TEGRA194_RESET_I2C4>;
568 			clocks = <&bpmp TEGRA194_CLK_I2C6>;
570 			resets = <&bpmp TEGRA194_RESET_I2C6>;
585 			clocks = <&bpmp TEGRA194_CLK_I2C7>;
587 			resets = <&bpmp TEGRA194_RESET_I2C7>;
602 			clocks = <&bpmp TEGRA194_CLK_I2C9>;
604 			resets = <&bpmp TEGRA194_RESET_I2C9>;
616 			clocks = <&bpmp TEGRA194_CLK_PWM1>;
618 			resets = <&bpmp TEGRA194_RESET_PWM1>;
628 			clocks = <&bpmp TEGRA194_CLK_PWM2>;
630 			resets = <&bpmp TEGRA194_RESET_PWM2>;
640 			clocks = <&bpmp TEGRA194_CLK_PWM3>;
642 			resets = <&bpmp TEGRA194_RESET_PWM3>;
652 			clocks = <&bpmp TEGRA194_CLK_PWM5>;
654 			resets = <&bpmp TEGRA194_RESET_PWM5>;
664 			clocks = <&bpmp TEGRA194_CLK_PWM6>;
666 			resets = <&bpmp TEGRA194_RESET_PWM6>;
676 			clocks = <&bpmp TEGRA194_CLK_PWM7>;
678 			resets = <&bpmp TEGRA194_RESET_PWM7>;
688 			clocks = <&bpmp TEGRA194_CLK_PWM8>;
690 			resets = <&bpmp TEGRA194_RESET_PWM8>;
700 			clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
701 				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
703 			resets = <&bpmp TEGRA194_RESET_SDMMC1>;
726 			clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
727 				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
729 			resets = <&bpmp TEGRA194_RESET_SDMMC3>;
753 			clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
754 				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
756 			assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
757 					  <&bpmp TEGRA194_CLK_PLLC4>;
759 					  <&bpmp TEGRA194_CLK_PLLC4>;
760 			resets = <&bpmp TEGRA194_RESET_SDMMC4>;
784 			clocks = <&bpmp TEGRA194_CLK_HDA>,
785 				 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
786 				 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
788 			resets = <&bpmp TEGRA194_RESET_HDA>,
789 				 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
791 			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
804 			resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
811 					clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
911 			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
912 				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
913 				 <&bpmp TEGRA194_CLK_XUSB_SS>,
914 				 <&bpmp TEGRA194_CLK_XUSB_FS>;
916 			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
917 					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
932 			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
933 				 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
934 				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
935 				 <&bpmp TEGRA194_CLK_XUSB_SS>,
936 				 <&bpmp TEGRA194_CLK_CLK_M>,
937 				 <&bpmp TEGRA194_CLK_XUSB_FS>,
938 				 <&bpmp TEGRA194_CLK_UTMIPLL>,
939 				 <&bpmp TEGRA194_CLK_CLK_M>,
940 				 <&bpmp TEGRA194_CLK_PLLE>;
946 			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
947 					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
957 			clocks = <&bpmp TEGRA194_CLK_FUSE>;
978 			clocks = <&bpmp TEGRA194_CLK_CEC>;
1182 			clocks = <&bpmp TEGRA194_CLK_I2C2>;
1184 			resets = <&bpmp TEGRA194_RESET_I2C2>;
1195 			clocks = <&bpmp TEGRA194_CLK_I2C8>;
1197 			resets = <&bpmp TEGRA194_RESET_I2C8>;
1207 			clocks = <&bpmp TEGRA194_CLK_UARTC>;
1209 			resets = <&bpmp TEGRA194_RESET_UARTC>;
1219 			clocks = <&bpmp TEGRA194_CLK_UARTG>;
1221 			resets = <&bpmp TEGRA194_RESET_UARTG>;
1231 			clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1252 			clocks = <&bpmp TEGRA194_CLK_PWM4>;
1254 			resets = <&bpmp TEGRA194_RESET_PWM4>;
1281 			clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1283 			resets = <&bpmp TEGRA194_RESET_HOST1X>;
1296 				resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1297 					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1298 					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1299 					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1300 					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1301 					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1302 					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1305 				clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1306 					 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1310 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1321 					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1323 					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1326 					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1339 					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1341 					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1344 					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1357 					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1359 					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1362 					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1375 					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1377 					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1380 					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1394 				clocks = <&bpmp TEGRA194_CLK_VIC>;
1396 				resets = <&bpmp TEGRA194_RESET_VIC>;
1399 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1409 				clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1410 					 <&bpmp TEGRA194_CLK_PLLDP>;
1412 				resets = <&bpmp TEGRA194_RESET_DPAUX>;
1416 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1443 				clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1444 					 <&bpmp TEGRA194_CLK_PLLDP>;
1446 				resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1450 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1477 				clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1478 					 <&bpmp TEGRA194_CLK_PLLDP>;
1480 				resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1484 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1511 				clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1512 					 <&bpmp TEGRA194_CLK_PLLDP>;
1514 				resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1518 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1545 				clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1546 					 <&bpmp TEGRA194_CLK_SOR0_OUT>,
1547 					 <&bpmp TEGRA194_CLK_PLLD>,
1548 					 <&bpmp TEGRA194_CLK_PLLDP>,
1549 					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1550 					 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1553 				resets = <&bpmp TEGRA194_RESET_SOR0>;
1561 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1569 				clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1570 					 <&bpmp TEGRA194_CLK_SOR1_OUT>,
1571 					 <&bpmp TEGRA194_CLK_PLLD2>,
1572 					 <&bpmp TEGRA194_CLK_PLLDP>,
1573 					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1574 					 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1577 				resets = <&bpmp TEGRA194_RESET_SOR1>;
1585 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1593 				clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1594 					 <&bpmp TEGRA194_CLK_SOR2_OUT>,
1595 					 <&bpmp TEGRA194_CLK_PLLD3>,
1596 					 <&bpmp TEGRA194_CLK_PLLDP>,
1597 					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1598 					 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1601 				resets = <&bpmp TEGRA194_RESET_SOR2>;
1609 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1617 				clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1618 					 <&bpmp TEGRA194_CLK_SOR3_OUT>,
1619 					 <&bpmp TEGRA194_CLK_PLLD4>,
1620 					 <&bpmp TEGRA194_CLK_PLLDP>,
1621 					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1622 					 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1625 				resets = <&bpmp TEGRA194_RESET_SOR3>;
1633 				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1645 			clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
1646 				 <&bpmp TEGRA194_CLK_GPU_PWR>,
1647 				 <&bpmp TEGRA194_CLK_FUSE>;
1649 			resets = <&bpmp TEGRA194_RESET_GPU>;
1653 			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
1675 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1691 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1694 		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1695 			 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1706 		nvidia,bpmp = <&bpmp 1>;
1725 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1741 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1744 		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1745 			 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1756 		nvidia,bpmp = <&bpmp 2>;
1775 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1791 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1794 		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1795 			 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1806 		nvidia,bpmp = <&bpmp 3>;
1825 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1841 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1844 		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1845 			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1856 		nvidia,bpmp = <&bpmp 4>;
1875 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1891 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1894 		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1895 			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1906 		nvidia,bpmp = <&bpmp 0>;
1925 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1944 		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
1945 			 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
1948 		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1949 			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1956 		nvidia,bpmp = <&bpmp 5>;
1979 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1992 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1995 		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1996 			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2002 		nvidia,bpmp = <&bpmp 4>;
2011 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2024 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2027 		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2028 			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2034 		nvidia,bpmp = <&bpmp 0>;
2043 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2059 		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2062 		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2063 			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2069 		nvidia,bpmp = <&bpmp 5>;
2085 			label = "cpu-bpmp-tx";
2091 			label = "cpu-bpmp-rx";
2096 	bpmp: bpmp {  label
2097 		compatible = "nvidia,tegra186-bpmp";
2111 			compatible = "nvidia,tegra186-bpmp-i2c";
2112 			nvidia,bpmp-bus-id = <5>;
2118 			compatible = "nvidia,tegra186-bpmp-thermal";
2125 		nvidia,bpmp = <&bpmp>;
2333 			thermal-sensors = <&{/bpmp/thermal}
2339 			thermal-sensors = <&{/bpmp/thermal}
2345 			thermal-sensors = <&{/bpmp/thermal}
2351 			thermal-sensors = <&{/bpmp/thermal}
2357 			thermal-sensors = <&{/bpmp/thermal}
2363 			thermal-sensors = <&{/bpmp/thermal}