Lines Matching full:bpmp
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
79 clocks = <&bpmp TEGRA186_CLK_APE>,
80 <&bpmp TEGRA186_CLK_APB2APE>;
82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
125 clocks = <&bpmp TEGRA186_CLK_AHUB>;
139 clocks = <&bpmp TEGRA186_CLK_APE>;
147 clocks = <&bpmp TEGRA186_CLK_AHUB>;
149 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
206 clocks = <&bpmp TEGRA186_CLK_I2S1>,
207 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
209 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
220 clocks = <&bpmp TEGRA186_CLK_I2S2>,
221 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
223 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
234 clocks = <&bpmp TEGRA186_CLK_I2S3>,
235 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
237 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
248 clocks = <&bpmp TEGRA186_CLK_I2S4>,
249 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
262 clocks = <&bpmp TEGRA186_CLK_I2S5>,
263 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
276 clocks = <&bpmp TEGRA186_CLK_I2S6>,
277 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
289 clocks = <&bpmp TEGRA186_CLK_DMIC1>;
291 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
292 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
301 clocks = <&bpmp TEGRA186_CLK_DMIC2>;
303 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
304 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
313 clocks = <&bpmp TEGRA186_CLK_DMIC3>;
315 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
316 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
325 clocks = <&bpmp TEGRA186_CLK_DMIC4>;
327 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
328 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
337 clocks = <&bpmp TEGRA186_CLK_DSPK1>;
339 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
340 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
349 clocks = <&bpmp TEGRA186_CLK_DSPK2>;
351 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
352 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
382 clocks = <&bpmp TEGRA186_CLK_EMC>;
387 nvidia,bpmp = <&bpmp>;
396 clocks = <&bpmp TEGRA186_CLK_UARTA>;
398 resets = <&bpmp TEGRA186_RESET_UARTA>;
408 clocks = <&bpmp TEGRA186_CLK_UARTB>;
410 resets = <&bpmp TEGRA186_RESET_UARTB>;
420 clocks = <&bpmp TEGRA186_CLK_UARTD>;
422 resets = <&bpmp TEGRA186_RESET_UARTD>;
432 clocks = <&bpmp TEGRA186_CLK_UARTE>;
434 resets = <&bpmp TEGRA186_RESET_UARTE>;
444 clocks = <&bpmp TEGRA186_CLK_UARTF>;
446 resets = <&bpmp TEGRA186_RESET_UARTF>;
457 clocks = <&bpmp TEGRA186_CLK_I2C1>;
459 resets = <&bpmp TEGRA186_RESET_I2C1>;
470 clocks = <&bpmp TEGRA186_CLK_I2C3>;
472 resets = <&bpmp TEGRA186_RESET_I2C3>;
484 clocks = <&bpmp TEGRA186_CLK_I2C4>;
486 resets = <&bpmp TEGRA186_RESET_I2C4>;
494 /* controlled by BPMP, should not be enabled */
501 clocks = <&bpmp TEGRA186_CLK_I2C5>;
503 resets = <&bpmp TEGRA186_RESET_I2C5>;
515 clocks = <&bpmp TEGRA186_CLK_I2C6>;
517 resets = <&bpmp TEGRA186_RESET_I2C6>;
531 clocks = <&bpmp TEGRA186_CLK_I2C7>;
533 resets = <&bpmp TEGRA186_RESET_I2C7>;
544 clocks = <&bpmp TEGRA186_CLK_I2C9>;
546 resets = <&bpmp TEGRA186_RESET_I2C9>;
555 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
556 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
558 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
575 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
576 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
577 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
585 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
586 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
588 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
610 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
611 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
613 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
637 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
638 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
640 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
641 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
642 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
643 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
667 clocks = <&bpmp TEGRA186_CLK_HDA>,
668 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
669 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
671 resets = <&bpmp TEGRA186_RESET_HDA>,
672 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
673 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
675 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
689 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
696 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
719 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
791 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
792 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
793 <&bpmp TEGRA186_CLK_XUSB_SS>,
794 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
795 <&bpmp TEGRA186_CLK_CLK_M>,
796 <&bpmp TEGRA186_CLK_XUSB_FS>,
797 <&bpmp TEGRA186_CLK_PLLU>,
798 <&bpmp TEGRA186_CLK_CLK_M>,
799 <&bpmp TEGRA186_CLK_PLLE>;
803 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
804 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
823 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
824 <&bpmp TEGRA186_CLK_XUSB_SS>,
825 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
826 <&bpmp TEGRA186_CLK_XUSB_FS>;
829 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
830 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
839 clocks = <&bpmp TEGRA186_CLK_FUSE>;
858 clocks = <&bpmp TEGRA186_CLK_CEC>;
878 clocks = <&bpmp TEGRA186_CLK_I2C2>;
880 resets = <&bpmp TEGRA186_RESET_I2C2>;
891 clocks = <&bpmp TEGRA186_CLK_I2C8>;
893 resets = <&bpmp TEGRA186_RESET_I2C8>;
903 clocks = <&bpmp TEGRA186_CLK_UARTC>;
905 resets = <&bpmp TEGRA186_RESET_UARTC>;
915 clocks = <&bpmp TEGRA186_CLK_UARTG>;
917 resets = <&bpmp TEGRA186_RESET_UARTG>;
927 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
990 nvidia,bpmp = <&bpmp>;
995 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1021 clocks = <&bpmp TEGRA186_CLK_PCIE>,
1022 <&bpmp TEGRA186_CLK_AFI>,
1023 <&bpmp TEGRA186_CLK_PLLE>;
1026 resets = <&bpmp TEGRA186_RESET_PCIE>,
1027 <&bpmp TEGRA186_RESET_AFI>,
1028 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1162 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1164 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1181 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1182 <&bpmp TEGRA186_CLK_PLLDP>;
1184 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1188 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1214 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1215 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1216 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1217 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1218 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1219 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1220 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1223 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1224 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1225 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1229 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1240 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1242 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1245 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1259 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1261 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1264 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1278 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1280 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1283 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1298 clocks = <&bpmp TEGRA186_CLK_DSI>,
1299 <&bpmp TEGRA186_CLK_DSIA_LP>,
1300 <&bpmp TEGRA186_CLK_PLLD>;
1302 resets = <&bpmp TEGRA186_RESET_DSI>;
1306 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1313 clocks = <&bpmp TEGRA186_CLK_VIC>;
1315 resets = <&bpmp TEGRA186_RESET_VIC>;
1318 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1329 clocks = <&bpmp TEGRA186_CLK_DSIB>,
1330 <&bpmp TEGRA186_CLK_DSIB_LP>,
1331 <&bpmp TEGRA186_CLK_PLLD>;
1333 resets = <&bpmp TEGRA186_RESET_DSIB>;
1337 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1344 clocks = <&bpmp TEGRA186_CLK_SOR0>,
1345 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1346 <&bpmp TEGRA186_CLK_PLLD2>,
1347 <&bpmp TEGRA186_CLK_PLLDP>,
1348 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1349 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1352 resets = <&bpmp TEGRA186_RESET_SOR0>;
1360 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1368 clocks = <&bpmp TEGRA186_CLK_SOR1>,
1369 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1370 <&bpmp TEGRA186_CLK_PLLD3>,
1371 <&bpmp TEGRA186_CLK_PLLDP>,
1372 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1373 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1376 resets = <&bpmp TEGRA186_RESET_SOR1>;
1384 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1392 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1393 <&bpmp TEGRA186_CLK_PLLDP>;
1395 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1399 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1425 resets = <&bpmp TEGRA186_RESET_DSI>;
1434 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1435 <&bpmp TEGRA186_CLK_DSIC_LP>,
1436 <&bpmp TEGRA186_CLK_PLLD>;
1438 resets = <&bpmp TEGRA186_RESET_DSIC>;
1442 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1449 clocks = <&bpmp TEGRA186_CLK_DSID>,
1450 <&bpmp TEGRA186_CLK_DSID_LP>,
1451 <&bpmp TEGRA186_CLK_PLLD>;
1453 resets = <&bpmp TEGRA186_RESET_DSID>;
1457 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1469 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1470 <&bpmp TEGRA186_CLK_GPU>;
1472 resets = <&bpmp TEGRA186_RESET_GPU>;
1476 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1493 label = "cpu-bpmp-tx";
1499 label = "cpu-bpmp-rx";
1504 bpmp: bpmp { label
1505 compatible = "nvidia,tegra186-bpmp";
1520 compatible = "nvidia,tegra186-bpmp-i2c";
1521 nvidia,bpmp-bus-id = <5>;
1528 compatible = "nvidia,tegra186-bpmp-thermal";