dts/mediatek/mt8173.dtsi

356 		topckgen: clock-controller@10000000 {  label
357 			compatible = "mediatek,mt8173-topckgen";
458 				 <&topckgen CLK_TOP_MM_SEL>,
459 				 <&topckgen CLK_TOP_VENC_SEL>,
460 				 <&topckgen CLK_TOP_VENC_LT_SEL>;
477 				 <&topckgen CLK_TOP_RTC_SEL>;
505 			clocks = <&topckgen CLK_TOP_SCP_SEL>;
703 			clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
704 				 <&topckgen CLK_TOP_SPI_SEL>,
728 				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
797 				 <&topckgen CLK_TOP_AUDIO_SEL>,
798 				 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
799 				 <&topckgen CLK_TOP_APLL1_DIV0>,
800 				 <&topckgen CLK_TOP_APLL2_DIV0>,
801 				 <&topckgen CLK_TOP_I2S0_M_SEL>,
802 				 <&topckgen CLK_TOP_I2S1_M_SEL>,
803 				 <&topckgen CLK_TOP_I2S2_M_SEL>,
804 				 <&topckgen CLK_TOP_I2S3_M_SEL>,
805 				 <&topckgen CLK_TOP_I2S3_B_SEL>;
816 			assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
817 					  <&topckgen CLK_TOP_AUD_2_SEL>;
818 			assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
819 						 <&topckgen CLK_TOP_APLL2>;
827 				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
837 				 <&topckgen CLK_TOP_AXI_SEL>;
847 				 <&topckgen CLK_TOP_AXI_SEL>;
857 				 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
872 			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
886 				clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
929 			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
1266 			assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1343 				 <&topckgen CLK_TOP_UNIVPLL_D2>,
1344 				 <&topckgen CLK_TOP_CCI400_SEL>,
1345 				 <&topckgen CLK_TOP_VDEC_SEL>,
1346 				 <&topckgen CLK_TOP_VCODECPLL>,
1348 				 <&topckgen CLK_TOP_VENC_LT_SEL>,
1349 				 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1358 			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1359 					  <&topckgen CLK_TOP_CCI400_SEL>,
1360 					  <&topckgen CLK_TOP_VDEC_SEL>,
1363 			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1364 						 <&topckgen CLK_TOP_UNIVPLL_D2>,
1365 						 <&topckgen CLK_TOP_VCODECPLL>;
1424 			clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1425 				 <&topckgen CLK_TOP_VENC_SEL>,
1426 				 <&topckgen CLK_TOP_UNIVPLL1_D2>,
1427 				 <&topckgen CLK_TOP_VENC_LT_SEL>;
1432 			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
1433 					  <&topckgen CLK_TOP_VENC_LT_SEL>;
1434 			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
1435 						 <&topckgen CLK_TOP_VCODECPLL_370P5>;