Lines Matching full:mmsys
925 mmsys: syscon@14000000 { label
926 compatible = "mediatek,mt8173-mmsys", "syscon";
941 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
942 <&mmsys CLK_MM_MUTEX_32K>;
952 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
953 <&mmsys CLK_MM_MUTEX_32K>;
962 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
969 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
976 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
983 clocks = <&mmsys CLK_MM_MDP_WDMA>;
992 clocks = <&mmsys CLK_MM_MDP_WROT0>;
1001 clocks = <&mmsys CLK_MM_MDP_WROT1>;
1012 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1023 clocks = <&mmsys CLK_MM_DISP_OVL1>;
1034 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1045 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1056 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1067 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1078 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1089 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1098 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1107 clocks = <&mmsys CLK_MM_DISP_AAL>;
1116 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1124 clocks = <&mmsys CLK_MM_DISP_MERGE>;
1131 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1138 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1146 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1154 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1155 <&mmsys CLK_MM_DSI0_DIGITAL>,
1168 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1169 <&mmsys CLK_MM_DSI1_DIGITAL>,
1182 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1183 <&mmsys CLK_MM_DPI_ENGINE>,
1200 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1201 <&mmsys CLK_MM_DISP_PWM0MM>;
1211 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1212 <&mmsys CLK_MM_DISP_PWM1MM>;
1222 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1232 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1233 <&mmsys CLK_MM_SMI_LARB0>;
1241 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1242 <&mmsys CLK_MM_SMI_COMMON>;
1249 clocks = <&mmsys CLK_MM_DISP_OD>;
1256 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1257 <&mmsys CLK_MM_HDMI_PLLCK>,
1258 <&mmsys CLK_MM_HDMI_AUDIO>,
1259 <&mmsys CLK_MM_HDMI_SPDIF>;
1265 mediatek,syscon-hdmi = <&mmsys 0x900>;
1289 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1290 <&mmsys CLK_MM_SMI_LARB4>;