Lines Matching +full:0 +full:x10011000
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
154 #clock-cells = <0>;
160 #clock-cells = <0>;
163 clk26m: oscillator@0 {
165 #clock-cells = <0>;
172 #clock-cells = <0>;
179 #clock-cells = <0>;
186 #clock-cells = <0>;
193 #clock-cells = <0>;
200 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
221 #clock-cells = <0>;
228 #clock-cells = <0>;
237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
243 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
248 reg = <0 0x10000000 0 0x1000>;
254 reg = <0 0x10001000 0 0x1000>;
260 reg = <0 0x10003000 0 0x1000>;
266 reg = <0 0x10005000 0 0x1000>;
271 reg = <0 0x1000b000 0 0x1000>;
284 reg = <0 0x10006000 0 0x1000>;
299 reg = <0 0x1000f000 0 0x400>;
311 reg = <0 0x10011000 0 0x1000>;
317 reg = <0 0x10013000 0 0x100>;
328 reg = <0 0x10205000 0 0x1000>;
339 reg = <0 0x10209000 0 0x1000>;
345 reg = <0 0x1020a000 0 0x1000>;
355 reg = <0 0x10220000 0 0x1000>;
365 reg = <0 0x10220a80 0 0x40>;
373 reg = <0 0x10510000 0 0x10000>,
374 <0 0x10520000 0 0x20000>,
375 <0 0x10540000 0 0x20000>,
376 <0 0x10560000 0 0x20000>;
378 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
384 reg = <0 0x11000400 0 0x80>,
385 <0 0x11000480 0 0x80>,
386 <0 0x11000500 0 0x80>,
387 <0 0x11000580 0 0x80>,
388 <0 0x11000600 0 0x80>,
389 <0 0x11000680 0 0x80>,
390 <0 0x11000700 0 0x80>,
391 <0 0x11000780 0 0x80>,
392 <0 0x11000800 0 0x80>,
393 <0 0x11000880 0 0x80>,
394 <0 0x11000900 0 0x80>,
395 <0 0x11000980 0 0x80>;
416 reg = <0 0x11001000 0 0x1000>;
426 reg = <0 0x11002000 0 0x400>;
430 dmas = <&apdma 0
439 reg = <0 0x11003000 0 0x400>;
452 reg = <0 0x11004000 0 0x400>;
465 reg = <0 0x11005000 0 0x400>;
477 reg = <0 0x11006000 0 0x1000>;
505 reg = <0 0x11007000 0 0x90>,
506 <0 0x11000180 0 0x80>;
514 #size-cells = <0>;
520 reg = <0 0x11008000 0 0x90>,
521 <0 0x11000200 0 0x80>;
529 #size-cells = <0>;
535 reg = <0 0x11009000 0 0x90>,
536 <0 0x11000280 0 0x80>;
544 #size-cells = <0>;
551 #size-cells = <0>;
552 reg = <0 0x1100a000 0 0x100>;
563 reg = <0 0x1100e000 0 0x1000>;
569 #size-cells = <0>;
575 reg = <0 0x1100f000 0 0x1000>;
584 reg = <0 0x11010000 0 0x90>,
585 <0 0x11000300 0 0x80>;
593 #size-cells = <0>;
599 reg = <0 0x11011000 0 0x90>,
600 <0 0x11000380 0 0x80>;
608 #size-cells = <0>;
614 reg = <0 0x11013000 0 0x90>,
615 <0 0x11000100 0 0x80>;
623 #size-cells = <0>;
630 #size-cells = <0>;
631 reg = <0 0x11015000 0 0x100>;
643 #size-cells = <0>;
644 reg = <0 0x11016000 0 0x100>;
656 #size-cells = <0>;
657 reg = <0 0x10012000 0 0x100>;
669 #size-cells = <0>;
670 reg = <0 0x11018000 0 0x100>;
682 reg = <0 0x11019000 0 0x400>;
693 snps,wr_osr_lmt = <0x7>;
694 snps,rd_osr_lmt = <0x7>;
695 snps,blen = <0 0 0 0 16 8 4>;
703 snps,map-to-dma-channel = <0x0>;
704 snps,priority = <0x0>;
712 snps,weight = <0x10>;
714 snps,priority = <0x0>;
717 snps,weight = <0x11>;
719 snps,priority = <0x1>;
722 snps,weight = <0x12>;
724 snps,priority = <0x2>;
730 reg = <0 0x1101c000 0 0x1300>;
753 clk_csr = <0>;
759 reg = <0 0x11230000 0 0x1000>;
771 reg = <0 0x11240000 0 0x1000>;
782 reg = <0 0x11250000 0 0x1000>;
793 reg = <0 0x11271000 0 0x3000>,
794 <0 0x11280700 0 0x0100>;
802 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
811 reg = <0 0x11270000 0 0x1000>;
826 ranges = <0 0 0x11290000 0x9000>;
829 u2port0: usb-phy@0 {
830 reg = <0x0 0x700>;
838 reg = <0x8000 0x700>;
846 reg = <0x8700 0x900>;
856 reg = <0 0x112c1000 0 0x3000>,
857 <0 0x112d0700 0 0x0100>;
866 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
875 reg = <0 0x112c0000 0 0x1000>;
890 ranges = <0 0 0x112e0000 0x9000>;
893 u2port2: usb-phy@0 {
894 reg = <0x0 0x700>;
902 reg = <0x8000 0x700>;
910 reg = <0x8700 0x900>;
921 reg = <0 0x11700000 0 0x1000>,
922 <0 0x112ff000 0 0x1000>;
935 bus-range = <0x00 0xff>;
936 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
938 pcie0: pcie@0,0 {
941 reg = <0x0000 0 0 0 0>;
946 interrupt-map-mask = <0 0 0 7>;
947 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
948 <0 0 0 2 &pcie_intc0 1>,
949 <0 0 0 3 &pcie_intc0 2>,
950 <0 0 0 4 &pcie_intc0 3>;
953 #address-cells = <0>;
958 pcie1: pcie@1,0 {
961 reg = <0x0800 0 0 0 0>;
966 interrupt-map-mask = <0 0 0 7>;
967 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
968 <0 0 0 2 &pcie_intc1 1>,
969 <0 0 0 3 &pcie_intc1 2>,
970 <0 0 0 4 &pcie_intc1 3>;
973 #address-cells = <0>;
981 reg = <0 0x13000000 0 0x1000>;
987 reg = <0 0x14000000 0 0x1000>;
993 reg = <0 0x14021000 0 0x1000>;
995 mediatek,larb-id = <0>;
1004 reg = <0 0x14022000 0 0x1000>;
1013 reg = <0 0x14027000 0 0x1000>;
1024 reg = <0 0x14030000 0 0x1000>;
1035 reg = <0 0x14031000 0 0x1000>;
1044 reg = <0 0x14032000 0 0x1000>;
1055 reg = <0 0x15000000 0 0x1000>;
1061 reg = <0 0x15001000 0 0x1000>;
1072 reg = <0 0x15010000 0 0x1000>;
1078 reg = <0 0x16000000 0 0x1000>;
1084 reg = <0 0x16010000 0 0x1000>;
1095 reg = <0 0x18000000 0 0x1000>;
1101 reg = <0 0x18001000 0 0x1000>;
1112 reg = <0 0x18002000 0 0x1000>;
1123 reg = <0 0x19000000 0 0x1000>;