Lines Matching +full:0 +full:x028
16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
36 0x70c MUX_M2 /* UART2_TXD */
42 0x064 MUX_M1 /* UART3_CTS_N */
43 0x068 MUX_M1 /* UART3_RTS_N */
44 0x06c MUX_M1 /* UART3_RXD */
45 0x070 MUX_M1 /* UART3_TXD */
51 0x074 MUX_M1 /* UART4_CTS_N */
52 0x078 MUX_M1 /* UART4_RTS_N */
53 0x07c MUX_M1 /* UART4_RXD */
54 0x080 MUX_M1 /* UART4_TXD */
60 0x05c MUX_M1 /* UART6_RXD */
61 0x060 MUX_M1 /* UART6_TXD */
68 reg = <0x0 0xe896c800 0x0 0x72c>;
70 pinctrl-single,register-width = <0x20>;
74 0x058 0x0 /* UART0_RXD */
75 0x05c 0x0 /* UART0_TXD */
96 0x700 0x0 /* UART2_CTS_N */
97 0x704 0x0 /* UART2_RTS_N */
98 0x708 0x0 /* UART2_RXD */
99 0x70c 0x0 /* UART2_TXD */
120 0x068 0x0 /* UART3_CTS_N */
121 0x06c 0x0 /* UART3_RTS_N */
122 0x070 0x0 /* UART3_RXD */
123 0x074 0x0 /* UART3_TXD */
144 0x078 0x0 /* UART4_CTS_N */
145 0x07c 0x0 /* UART4_RTS_N */
146 0x080 0x0 /* UART4_RXD */
147 0x084 0x0 /* UART4_TXD */
168 0x060 0x0 /* UART6_RXD */
169 0x064 0x0 /* UART6_TXD */
191 reg = <0x0 0xfc182000 0x0 0x028>;
194 pinctrl-single,register-width = <0x20>;
195 pinctrl-single,function-mask = <0x7>;
197 pinctrl-single,gpio-range = <&range 0 10 0>;
201 0x000 MUX_M1 /* SDIO_CLK */
202 0x004 MUX_M1 /* SDIO_CMD */
203 0x008 MUX_M1 /* SDIO_DATA0 */
204 0x00c MUX_M1 /* SDIO_DATA1 */
205 0x010 MUX_M1 /* SDIO_DATA2 */
206 0x014 MUX_M1 /* SDIO_DATA3 */
213 reg = <0x0 0xfc182800 0x0 0x028>;
215 pinctrl-single,register-width = <0x20>;
219 0x000 0x0 /* SDIO_CLK */
240 0x004 0x0 /* SDIO_CMD */
241 0x008 0x0 /* SDIO_DATA0 */
242 0x00c 0x0 /* SDIO_DATA1 */
243 0x010 0x0 /* SDIO_DATA2 */
244 0x014 0x0 /* SDIO_DATA3 */
266 reg = <0x0 0xff37e000 0x0 0x030>;
269 pinctrl-single,register-width = <0x20>;
272 pinctrl-single,gpio-range = <&range 0 12 0>;
276 0x000 MUX_M1 /* SD_CLK */
277 0x004 MUX_M1 /* SD_CMD */
278 0x008 MUX_M1 /* SD_DATA0 */
279 0x00c MUX_M1 /* SD_DATA1 */
280 0x010 MUX_M1 /* SD_DATA2 */
281 0x014 MUX_M1 /* SD_DATA3 */
288 reg = <0x0 0xff37e800 0x0 0x030>;
290 pinctrl-single,register-width = <0x20>;
294 0x000 0x0 /* SD_CLK */
316 0x004 0x0 /* SD_CMD */
317 0x008 0x0 /* SD_DATA0 */
318 0x00c 0x0 /* SD_DATA1 */
319 0x010 0x0 /* SD_DATA2 */
320 0x014 0x0 /* SD_DATA3 */
343 reg = <0x0 0xfff11000 0x0 0x73c>;
344 #gpio-range-cells = <0x3>;
346 pinctrl-single,register-width = <0x20>;
347 pinctrl-single,function-mask = <0x7>;
349 pinctrl-single,gpio-range = <&range 0 46 0>;
354 reg = <0x0 0xfff11800 0x0 0x73c>;
356 pinctrl-single,register-width = <0x20>;