dts/hisilicon/hi3798cv200.dtsi

85 		crg: clock-reset-controller@8a22000 {  label
86 			compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
120 				clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
121 				resets = <&crg 0xbc 4>;
128 					resets = <&crg 0xbc 8>;
134 					resets = <&crg 0xbc 9>;
141 				clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
142 				resets = <&crg 0xbc 6>;
149 					resets = <&crg 0xbc 10>;
157 				clocks = <&crg HISTB_COMBPHY0_CLK>;
158 				resets = <&crg 0x188 4>;
159 				assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
168 				clocks = <&crg HISTB_COMBPHY1_CLK>;
169 				resets = <&crg 0x188 12>;
170 				assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
229 			clocks = <&crg HISTB_UART2_CLK>;
241 			clocks = <&crg HISTB_I2C0_CLK>;
252 			clocks = <&crg HISTB_I2C1_CLK>;
263 			clocks = <&crg HISTB_I2C2_CLK>;
274 			clocks = <&crg HISTB_I2C3_CLK>;
285 			clocks = <&crg HISTB_I2C4_CLK>;
295 			clocks = <&crg HISTB_SPI0_CLK>;
306 			clocks = <&crg HISTB_SDIO0_CIU_CLK>,
307 				 <&crg HISTB_SDIO0_BIU_CLK>;
309 			resets = <&crg 0x9c 4>;
318 			clocks = <&crg HISTB_MMC_CIU_CLK>,
319 				 <&crg HISTB_MMC_BIU_CLK>,
320 				 <&crg HISTB_MMC_SAMPLE_CLK>,
321 				 <&crg HISTB_MMC_DRV_CLK>;
323 			resets = <&crg 0xa0 4>;
337 			clocks = <&crg HISTB_APB_CLK>;
357 			clocks = <&crg HISTB_APB_CLK>;
371 			clocks = <&crg HISTB_APB_CLK>;
390 			clocks = <&crg HISTB_APB_CLK>;
404 			clocks = <&crg HISTB_APB_CLK>;
417 			clocks = <&crg HISTB_APB_CLK>;
431 			clocks = <&crg HISTB_APB_CLK>;
445 			clocks = <&crg HISTB_APB_CLK>;
459 			clocks = <&crg HISTB_APB_CLK>;
473 			clocks = <&crg HISTB_APB_CLK>;
487 			clocks = <&crg HISTB_APB_CLK>;
501 			clocks = <&crg HISTB_APB_CLK>;
515 			clocks = <&crg HISTB_APB_CLK>;
525 			clocks = <&crg HISTB_ETH0_MAC_CLK>,
526 				 <&crg HISTB_ETH0_MACIF_CLK>;
528 			resets = <&crg 0xcc 8>,
529 				 <&crg 0xcc 10>,
540 			clocks = <&crg HISTB_ETH1_MAC_CLK>,
541 				 <&crg HISTB_ETH1_MACIF_CLK>;
543 			resets = <&crg 0xcc 9>,
544 				 <&crg 0xcc 11>,
576 			clocks = <&crg HISTB_PCIE_AUX_CLK>,
577 				 <&crg HISTB_PCIE_PIPE_CLK>,
578 				 <&crg HISTB_PCIE_SYS_CLK>,
579 				 <&crg HISTB_PCIE_BUS_CLK>;
581 			resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
592 			clocks = <&crg HISTB_USB2_BUS_CLK>,
593 				 <&crg HISTB_USB2_12M_CLK>,
594 				 <&crg HISTB_USB2_48M_CLK>;
596 			resets = <&crg 0xb8 12>;
607 			clocks = <&crg HISTB_USB2_BUS_CLK>,
608 				 <&crg HISTB_USB2_PHY_CLK>,
609 				 <&crg HISTB_USB2_UTMI_CLK>;
611 			resets = <&crg 0xb8 12>,
612 				 <&crg 0xb8 16>,
613 				 <&crg 0xb8 13>;