Lines Matching +full:0 +full:x18c
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x0 0x0>;
39 reg = <0x0 0x1>;
46 reg = <0x0 0x2>;
53 reg = <0x0 0x3>;
60 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
61 <0x0 0xf1002000 0x0 0x100>; /* GICC */
62 #address-cells = <0>;
83 ranges = <0x0 0x0 0xf0000000 0x10000000>;
87 reg = <0x8a22000 0x1000>;
95 <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
97 <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
104 reg = <0x8000000 0x1000>;
112 reg = <0x8a20000 0x1000>;
115 ranges = <0x0 0x8a20000 0x1000>;
119 reg = <0x120 0x4>;
121 resets = <&crg 0xbc 4>;
123 #size-cells = <0>;
125 usb2_phy1_port0: phy@0 {
126 reg = <0>;
127 #phy-cells = <0>;
128 resets = <&crg 0xbc 8>;
133 #phy-cells = <0>;
134 resets = <&crg 0xbc 9>;
140 reg = <0x124 0x4>;
142 resets = <&crg 0xbc 6>;
144 #size-cells = <0>;
146 usb2_phy2_port0: phy@0 {
147 reg = <0>;
148 #phy-cells = <0>;
149 resets = <&crg 0xbc 10>;
155 reg = <0x850 0x8>;
158 resets = <&crg 0x188 4>;
166 reg = <0x858 0x8>;
169 resets = <&crg 0x188 12>;
172 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
178 reg = <0x8a21000 0x180>;
182 &range 0 8 2 /* GPIO 0 */
183 &range 8 1 0 /* GPIO 1 */
185 &range 13 1 0
187 &range 15 1 0
188 &range 16 5 0 /* GPIO 2 */
193 &range 87 1 0
195 &range 34 3 0
198 &range 41 5 0
202 &range 71 1 0
204 &range 78 1 0
208 &range 88 8 0 /* GPIO 12 */
218 reg = <0x8b00000 0x1000>;
227 reg = <0x8b02000 0x1000>;
236 reg = <0x8b10000 0x1000>;
238 #size-cells = <0>;
247 reg = <0x8b11000 0x1000>;
249 #size-cells = <0>;
258 reg = <0x8b12000 0x1000>;
260 #size-cells = <0>;
269 reg = <0x8b13000 0x1000>;
271 #size-cells = <0>;
280 reg = <0x8b14000 0x1000>;
282 #size-cells = <0>;
291 reg = <0x8b1a000 0x1000>;
294 cs-gpios = <&gpio7 1 0>;
298 #size-cells = <0>;
304 reg = <0x9820000 0x10000>;
309 resets = <&crg 0x9c 4>;
316 reg = <0x9830000 0x10000>;
323 resets = <&crg 0xa0 4>;
330 reg = <0x8b20000 0x1000>;
336 gpio-ranges = <&pmx0 0 0 8>;
344 reg = <0x8b21000 0x1000>;
351 &pmx0 0 8 1
364 reg = <0x8b22000 0x1000>;
370 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
378 reg = <0x8b23000 0x1000>;
385 &pmx0 0 24 4
397 reg = <0x8b24000 0x1000>;
403 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
411 reg = <0x8004000 0x1000>;
424 reg = <0x8b26000 0x1000>;
430 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
438 reg = <0x8b27000 0x1000>;
444 gpio-ranges = <&pmx0 0 46 8>;
452 reg = <0x8b28000 0x1000>;
458 gpio-ranges = <&pmx0 0 54 8>;
466 reg = <0x8b29000 0x1000>;
472 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
480 reg = <0x8b2a000 0x1000>;
486 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
494 reg = <0x8b2b000 0x1000>;
500 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
508 reg = <0x8b2c000 0x1000>;
514 gpio-ranges = <&pmx0 0 88 8>;
522 reg = <0x9840000 0x1000>,
523 <0x984300c 0x4>;
528 resets = <&crg 0xcc 8>,
529 <&crg 0xcc 10>,
530 <&gmacphyrst 0>;
537 reg = <0x9841000 0x1000>,
538 <0x9843010 0x4>;
543 resets = <&crg 0xcc 9>,
544 <&crg 0xcc 11>,
552 reg = <0x8001000 0x1000>;
560 reg = <0x9860000 0x1000>,
561 <0x0 0x2000>,
562 <0x2000000 0x01000000>;
567 bus-range = <0x00 0xff>;
569 ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
570 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
574 interrupt-map-mask = <0 0 0 0>;
575 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
581 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
590 reg = <0x9880000 0x10000>;
596 resets = <&crg 0xb8 12>;
605 reg = <0x9890000 0x10000>;
611 resets = <&crg 0xb8 12>,
612 <&crg 0xb8 16>,
613 <&crg 0xb8 13>;