Lines Matching +full:0 +full:x49
21 pwms = <&pwm1 0 5000000>;
22 brightness-levels = <0 100>;
26 default-brightness-level = <0>;
37 pinctrl-0 = <&pinctrl_gpio_keys>;
73 pinctrl-0 = <&pinctrl_gpio_leds>;
84 #clock-cells = <0>;
140 pinctrl-0 = <&pinctrl_pwr_en>;
152 pinctrl-0 = <&pinctrl_usdhc2_pwr>;
163 #sound-dai-cells = <0>;
213 pinctrl-0 = <&pinctrl_haptic>;
221 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
258 pinctrl-0 = <&pinctrl_fec1>;
267 #size-cells = <0>;
279 pinctrl-0 = <&pinctrl_i2c1>;
284 reg = <0x4b>;
286 pinctrl-0 = <&pinctrl_pmic>;
289 #clock-cells = <0>;
416 reg = <0x52>;
418 pinctrl-0 = <&pinctrl_typec>;
440 #size-cells = <0>;
442 port@0 {
443 reg = <0>;
463 reg = <0x68>;
465 pinctrl-0 = <&pinctrl_rtc>;
472 reg = <0x6b>;
474 pinctrl-0 = <&pinctrl_charger>;
490 pinctrl-0 = <&pinctrl_i2c3>;
495 reg = <0x1e>;
497 pinctrl-0 = <&pinctrl_imu>;
510 #sound-dai-cells = <0>;
511 reg = <0x0a>;
519 reg = <0x5d>;
521 pinctrl-0 = <&pinctrl_ts>;
523 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
525 irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
534 reg = <0x60>;
535 pinctrl-0 = <&pinctrl_prox>;
540 reg = <0x6a>;
543 mount-matrix = "1", "0", "0",
544 "0", "1", "0",
545 "0", "0", "-1";
552 MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */
558 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */
559 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */
565 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */
571 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
572 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
573 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
574 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
575 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
576 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
577 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
578 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
579 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
580 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
581 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
582 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
583 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
584 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
585 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
586 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
592 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */
593 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */
599 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
605 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
606 MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
607 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */
608 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
614 MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */
620 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
621 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
627 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
628 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
634 MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */
640 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */
646 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */
652 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
658 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */
664 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
665 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
666 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
667 MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
668 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
674 MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
675 MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
676 MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
677 MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
683 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
684 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
690 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
691 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
697 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
698 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
699 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
700 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
706 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
707 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
713 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
714 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
715 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
716 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
717 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
723 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
724 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
725 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
726 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
727 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
728 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
729 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
730 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
731 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
732 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
733 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
734 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
740 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
741 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
742 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
743 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
744 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
745 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
746 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
747 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
748 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
749 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
750 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
751 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
757 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
758 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
759 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
760 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
761 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
762 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
763 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
764 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
765 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
766 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
767 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
768 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
774 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
780 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
786 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
787 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
788 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
789 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
790 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
791 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
797 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
798 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
799 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
800 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
801 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
802 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
808 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
809 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
810 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
811 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
812 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
813 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
819 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
825 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06
831 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */
832 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
833 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
845 #size-cells = <0>;
847 panel@0 {
849 reg = <0>;
881 pinctrl-0 = <&pinctrl_bl>;
891 pinctrl-0 = <&pinctrl_sai2>;
900 pinctrl-0 = <&pinctrl_sai6>;
910 pinctrl-0 = <&pinctrl_uart1>;
916 pinctrl-0 = <&pinctrl_uart3>;
922 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
939 #size-cells = <0>;
943 port@0 {
944 reg = <0>;
969 pinctrl-0 = <&pinctrl_usdhc1>;
981 pinctrl-0 = <&pinctrl_usdhc2>;
997 pinctrl-0 = <&pinctrl_wdog>;