Lines Matching +full:0 +full:x0000006a
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0x0>;
42 clocks = <&clockgen 1 0>;
51 reg = <0x1>;
52 clocks = <&clockgen 1 0>;
61 reg = <0x2>;
62 clocks = <&clockgen 1 0>;
71 reg = <0x3>;
72 clocks = <&clockgen 1 0>;
93 arm,psci-suspend-param = <0x0>;
103 reg = <0x0 0x80000000 0x0 0x0>;
108 #clock-cells = <0>;
116 offset = <0xb0>;
117 mask = <0x02>;
124 thermal-sensors = <&tmu 0>;
235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
237 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
239 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
241 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
261 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
262 <0x0 0x1420000 0 0x20000>, /* GICC */
263 <0x0 0x1440000 0 0x20000>, /* GICH */
264 <0x0 0x1460000 0 0x20000>; /* GICV */
265 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
277 reg = <0x0 0x1080000 0x0 0x1000>;
284 reg = <0x0 0x1530000 0x0 0x10000>;
292 #size-cells = <0>;
293 reg = <0x0 0x1550000 0x0 0x10000>,
294 <0x0 0x40000000 0x0 0x10000000>;
304 reg = <0x0 0x1560000 0x0 0x10000>;
315 reg = <0x0 0x1570000 0x0 0x10000>;
320 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
321 "fsl,sec-v4.0";
325 ranges = <0x0 0x00 0x1700000 0x100000>;
326 reg = <0x00 0x1700000 0x0 0x100000>;
332 "fsl,sec-v5.0-job-ring",
333 "fsl,sec-v4.0-job-ring";
334 reg = <0x10000 0x10000>;
340 "fsl,sec-v5.0-job-ring",
341 "fsl,sec-v4.0-job-ring";
342 reg = <0x20000 0x10000>;
348 "fsl,sec-v5.0-job-ring",
349 "fsl,sec-v4.0-job-ring";
350 reg = <0x30000 0x10000>;
356 "fsl,sec-v5.0-job-ring",
357 "fsl,sec-v4.0-job-ring";
358 reg = <0x40000 0x10000>;
365 reg = <0x0 0x1880000 0x0 0x10000>;
373 reg = <0x0 0x1890000 0x0 0x10000>;
380 ranges = <0x0 0x5 0x00000000 0x8000000>;
384 ranges = <0x0 0x5 0x08000000 0x8000000>;
389 reg = <0x0 0x1ee0000 0x0 0x1000>;
395 reg = <0x0 0x1ee1000 0x0 0x1000>;
402 reg = <0x0 0x1f00000 0x0 0x10000>;
403 interrupts = <0 33 0x4>;
404 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
407 <0x00000000 0x00000026
408 0x00000001 0x0000002d
409 0x00000002 0x00000032
410 0x00000003 0x00000039
411 0x00000004 0x0000003f
412 0x00000005 0x00000046
413 0x00000006 0x0000004d
414 0x00000007 0x00000054
415 0x00000008 0x0000005a
416 0x00000009 0x00000061
417 0x0000000a 0x0000006a
418 0x0000000b 0x00000071
420 0x00010000 0x00000025
421 0x00010001 0x0000002c
422 0x00010002 0x00000035
423 0x00010003 0x0000003d
424 0x00010004 0x00000045
425 0x00010005 0x0000004e
426 0x00010006 0x00000057
427 0x00010007 0x00000061
428 0x00010008 0x0000006b
429 0x00010009 0x00000076
431 0x00020000 0x00000029
432 0x00020001 0x00000033
433 0x00020002 0x0000003d
434 0x00020003 0x00000049
435 0x00020004 0x00000056
436 0x00020005 0x00000061
437 0x00020006 0x0000006d
439 0x00030000 0x00000021
440 0x00030001 0x0000002a
441 0x00030002 0x0000003c
442 0x00030003 0x0000004e>;
448 compatible = "fsl,ls1021a-v1.0-dspi";
450 #size-cells = <0>;
451 reg = <0x0 0x2100000 0x0 0x10000>;
463 #size-cells = <0>;
464 reg = <0x0 0x2180000 0x0 0x10000>;
476 #size-cells = <0>;
477 reg = <0x0 0x2190000 0x0 0x10000>;
486 #size-cells = <0>;
487 reg = <0x0 0x21a0000 0x0 0x10000>;
496 #size-cells = <0>;
497 reg = <0x0 0x21b0000 0x0 0x10000>;
505 reg = <0x00 0x21c0500 0x0 0x100>;
513 reg = <0x00 0x21c0600 0x0 0x100>;
521 reg = <0x0 0x21d0500 0x0 0x100>;
529 reg = <0x0 0x21d0600 0x0 0x100>;
537 reg = <0x0 0x2300000 0x0 0x10000>;
547 reg = <0x0 0x2310000 0x0 0x10000>;
557 reg = <0x0 0x2320000 0x0 0x10000>;
567 reg = <0x0 0x2330000 0x0 0x10000>;
577 reg = <0x0 0x2950000 0x0 0x1000>;
579 clocks = <&clockgen 4 0>;
586 reg = <0x0 0x2960000 0x0 0x1000>;
595 reg = <0x0 0x2970000 0x0 0x1000>;
604 reg = <0x0 0x2980000 0x0 0x1000>;
613 reg = <0x0 0x2990000 0x0 0x1000>;
622 reg = <0x0 0x29a0000 0x0 0x1000>;
631 reg = <0x0 0x2ad0000 0x0 0x10000>;
640 reg = <0x0 0x2c00000 0x0 0x10000>,
641 <0x0 0x2c10000 0x0 0x10000>,
642 <0x0 0x2c20000 0x0 0x10000>;
655 reg = <0x0 0x2f00000 0x0 0x10000>;
658 snps,quirk-frame-length-adjustment = <0x20>;
665 reg = <0x0 0x3000000 0x0 0x10000>;
668 snps,quirk-frame-length-adjustment = <0x20>;
675 reg = <0x0 0x3100000 0x0 0x10000>;
678 snps,quirk-frame-length-adjustment = <0x20>;
685 reg = <0x0 0x3200000 0x0 0x10000>,
686 <0x0 0x20140520 0x0 0x4>;
695 reg = <0x0 0x1580000 0x0 0x10000>;
705 reg = <0x0 0x1590000 0x0 0x10000>;
715 reg = <0x0 0x15a0000 0x0 0x10000>;
724 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
725 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
735 bus-range = <0x0 0xff>;
736 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
737 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
740 interrupt-map-mask = <0 0 0 7>;
741 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
742 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
743 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
744 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
750 reg = <0x00 0x03400000 0x0 0x00100000
751 0x40 0x00000000 0x8 0x00000000>;
760 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
761 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
771 bus-range = <0x0 0xff>;
772 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
773 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
776 interrupt-map-mask = <0 0 0 7>;
777 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
778 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
779 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
780 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
786 reg = <0x00 0x03500000 0x0 0x00100000
787 0x48 0x00000000 0x8 0x00000000>;
796 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
797 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
807 bus-range = <0x0 0xff>;
808 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
809 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
812 interrupt-map-mask = <0 0 0 7>;
813 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
814 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
815 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
816 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
822 reg = <0x00 0x03600000 0x0 0x00100000
823 0x50 0x00000000 0x8 0x00000000>;
832 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
833 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
834 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
844 block-offset = <0x10000>;
853 reg = <0x0 0x1ee2140 0x0 0x4>;
859 reg = <0x0 0x29d0000 0x0 0x10000>;
860 fsl,rcpm-wakeup = <&rcpm 0x20000>;
873 size = <0 0x1000000>;
874 alignment = <0 0x1000000>;
880 size = <0 0x800000>;
881 alignment = <0 0x800000>;
887 size = <0 0x2000000>;
888 alignment = <0 0x2000000>;