Lines Matching +full:0 +full:x0000006a
35 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0>;
47 clocks = <&clockgen 1 0>;
56 reg = <0x1>;
57 clocks = <&clockgen 1 0>;
66 reg = <0x2>;
67 clocks = <&clockgen 1 0>;
76 reg = <0x3>;
77 clocks = <&clockgen 1 0>;
98 arm,psci-suspend-param = <0x0>;
107 reg = <0x0 0x80000000 0 0x80000000>;
118 size = <0 0x1000000>;
119 alignment = <0 0x1000000>;
125 size = <0 0x400000>;
126 alignment = <0 0x400000>;
132 size = <0 0x2000000>;
133 alignment = <0 0x2000000>;
140 #clock-cells = <0>;
148 offset = <0xb0>;
149 mask = <0x02>;
156 thermal-sensors = <&tmu 0>;
267 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
268 <1 14 0xf08>, /* Physical Non-Secure PPI */
269 <1 11 0xf08>, /* Virtual PPI */
270 <1 10 0xf08>; /* Hypervisor PPI */
276 interrupts = <0 106 0x4>,
277 <0 107 0x4>,
278 <0 95 0x4>,
279 <0 97 0x4>;
290 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
291 <0x0 0x1402000 0 0x2000>, /* GICC */
292 <0x0 0x1404000 0 0x2000>, /* GICH */
293 <0x0 0x1406000 0 0x2000>; /* GICV */
294 interrupts = <1 9 0xf08>;
305 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 reg = <0x0 0x1570000 0x0 0x10000>;
317 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
318 "fsl,sec-v4.0";
322 ranges = <0x0 0x00 0x1700000 0x100000>;
323 reg = <0x00 0x1700000 0x0 0x100000>;
324 interrupts = <0 75 0x4>;
329 "fsl,sec-v5.0-job-ring",
330 "fsl,sec-v4.0-job-ring";
331 reg = <0x10000 0x10000>;
332 interrupts = <0 71 0x4>;
337 "fsl,sec-v5.0-job-ring",
338 "fsl,sec-v4.0-job-ring";
339 reg = <0x20000 0x10000>;
340 interrupts = <0 72 0x4>;
345 "fsl,sec-v5.0-job-ring",
346 "fsl,sec-v4.0-job-ring";
347 reg = <0x30000 0x10000>;
348 interrupts = <0 73 0x4>;
353 "fsl,sec-v5.0-job-ring",
354 "fsl,sec-v4.0-job-ring";
355 reg = <0x40000 0x10000>;
356 interrupts = <0 74 0x4>;
362 reg = <0x0 0x1ee0000 0x0 0x10000>;
368 reg = <0x0 0x1530000 0x0 0x10000>;
369 interrupts = <0 43 0x4>;
375 #size-cells = <0>;
376 reg = <0x0 0x1550000 0x0 0x10000>,
377 <0x0 0x40000000 0x0 0x4000000>;
379 interrupts = <0 99 0x4>;
381 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
387 reg = <0x0 0x1560000 0x0 0x10000>;
388 interrupts = <0 62 0x4>;
389 clock-frequency = <0>;
398 reg = <0x0 0x1080000 0x0 0x1000>;
399 interrupts = <0 144 0x4>;
405 reg = <0x0 0x1f00000 0x0 0x10000>;
406 interrupts = <0 33 0x4>;
407 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
408 fsl,tmu-calibration = <0x00000000 0x00000026
409 0x00000001 0x0000002d
410 0x00000002 0x00000032
411 0x00000003 0x00000039
412 0x00000004 0x0000003f
413 0x00000005 0x00000046
414 0x00000006 0x0000004d
415 0x00000007 0x00000054
416 0x00000008 0x0000005a
417 0x00000009 0x00000061
418 0x0000000a 0x0000006a
419 0x0000000b 0x00000071
421 0x00010000 0x00000025
422 0x00010001 0x0000002c
423 0x00010002 0x00000035
424 0x00010003 0x0000003d
425 0x00010004 0x00000045
426 0x00010005 0x0000004e
427 0x00010006 0x00000057
428 0x00010007 0x00000061
429 0x00010008 0x0000006b
430 0x00010009 0x00000076
432 0x00020000 0x00000029
433 0x00020001 0x00000033
434 0x00020002 0x0000003d
435 0x00020003 0x00000049
436 0x00020004 0x00000056
437 0x00020005 0x00000061
438 0x00020006 0x0000006d
440 0x00030000 0x00000021
441 0x00030001 0x0000002a
442 0x00030002 0x0000003c
443 0x00030003 0x0000004e>;
449 reg = <0x0 0x1880000 0x0 0x10000>;
456 reg = <0x0 0x1890000 0x0 0x10000>;
462 ranges = <0x0 0x5 0x08000000 0x8000000>;
466 ranges = <0x0 0x5 0x00000000 0x8000000>;
470 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
472 #size-cells = <0>;
473 reg = <0x0 0x2100000 0x0 0x10000>;
474 interrupts = <0 64 0x4>;
476 clocks = <&clockgen 4 0>;
483 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
485 #size-cells = <0>;
486 reg = <0x0 0x2110000 0x0 0x10000>;
487 interrupts = <0 65 0x4>;
489 clocks = <&clockgen 4 0>;
498 #size-cells = <0>;
499 reg = <0x0 0x2180000 0x0 0x10000>;
500 interrupts = <0 56 0x4>;
502 clocks = <&clockgen 4 0>;
512 #size-cells = <0>;
513 reg = <0x0 0x2190000 0x0 0x10000>;
514 interrupts = <0 57 0x4>;
516 clocks = <&clockgen 4 0>;
523 #size-cells = <0>;
524 reg = <0x0 0x21a0000 0x0 0x10000>;
525 interrupts = <0 58 0x4>;
527 clocks = <&clockgen 4 0>;
534 #size-cells = <0>;
535 reg = <0x0 0x21b0000 0x0 0x10000>;
536 interrupts = <0 59 0x4>;
538 clocks = <&clockgen 4 0>;
544 reg = <0x00 0x21c0500 0x0 0x100>;
545 interrupts = <0 54 0x4>;
546 clocks = <&clockgen 4 0>;
551 reg = <0x00 0x21c0600 0x0 0x100>;
552 interrupts = <0 54 0x4>;
553 clocks = <&clockgen 4 0>;
558 reg = <0x0 0x21d0500 0x0 0x100>;
559 interrupts = <0 55 0x4>;
560 clocks = <&clockgen 4 0>;
565 reg = <0x0 0x21d0600 0x0 0x100>;
566 interrupts = <0 55 0x4>;
567 clocks = <&clockgen 4 0>;
572 reg = <0x0 0x2300000 0x0 0x10000>;
573 interrupts = <0 66 0x4>;
582 reg = <0x0 0x2310000 0x0 0x10000>;
583 interrupts = <0 67 0x4>;
592 reg = <0x0 0x2320000 0x0 0x10000>;
593 interrupts = <0 68 0x4>;
602 reg = <0x0 0x2330000 0x0 0x10000>;
603 interrupts = <0 134 0x4>;
614 ranges = <0x0 0x0 0x2400000 0x40000>;
615 reg = <0x0 0x2400000 0x0 0x480>;
623 reg = <0x80 0x80>;
624 #address-cells = <0>;
633 #size-cells = <0>;
636 reg = <0x700 0x80>;
644 reg = <0x1000 0x800>;
649 reg = <0x2000 0x200>;
656 reg = <0x2200 0x200>;
665 ranges = <0x0 0x10000 0x6000>;
667 data-only@0 {
670 reg = <0x0 0x6000>;
677 reg = <0x0 0x2950000 0x0 0x1000>;
678 interrupts = <0 48 0x4>;
679 clocks = <&clockgen 0 0>;
686 reg = <0x0 0x2960000 0x0 0x1000>;
687 interrupts = <0 49 0x4>;
688 clocks = <&clockgen 4 0>;
695 reg = <0x0 0x2970000 0x0 0x1000>;
696 interrupts = <0 50 0x4>;
697 clocks = <&clockgen 4 0>;
704 reg = <0x0 0x2980000 0x0 0x1000>;
705 interrupts = <0 51 0x4>;
706 clocks = <&clockgen 4 0>;
713 reg = <0x0 0x2990000 0x0 0x1000>;
714 interrupts = <0 52 0x4>;
715 clocks = <&clockgen 4 0>;
722 reg = <0x0 0x29a0000 0x0 0x1000>;
723 interrupts = <0 53 0x4>;
724 clocks = <&clockgen 4 0>;
731 reg = <0x0 0x2ad0000 0x0 0x10000>;
732 interrupts = <0 83 0x4>;
733 clocks = <&clockgen 4 0>;
741 reg = <0x0 0x2c00000 0x0 0x10000>,
742 <0x0 0x2c10000 0x0 0x10000>,
743 <0x0 0x2c20000 0x0 0x10000>;
744 interrupts = <0 103 0x4>,
745 <0 103 0x4>;
750 clocks = <&clockgen 4 0>,
751 <&clockgen 4 0>;
756 reg = <0x0 0x2f00000 0x0 0x10000>;
757 interrupts = <0 60 0x4>;
759 snps,quirk-frame-length-adjustment = <0x20>;
767 reg = <0x0 0x3000000 0x0 0x10000>;
768 interrupts = <0 61 0x4>;
770 snps,quirk-frame-length-adjustment = <0x20>;
778 reg = <0x0 0x3100000 0x0 0x10000>;
779 interrupts = <0 63 0x4>;
781 snps,quirk-frame-length-adjustment = <0x20>;
789 reg = <0x0 0x3200000 0x0 0x10000>,
790 <0x0 0x20140520 0x0 0x4>;
792 interrupts = <0 69 0x4>;
793 clocks = <&clockgen 4 0>;
799 reg = <0x0 0x1571000 0x0 0x8>;
801 interrupts = <0 116 0x4>;
806 reg = <0x0 0x1572000 0x0 0x8>;
808 interrupts = <0 126 0x4>;
813 reg = <0x0 0x1573000 0x0 0x8>;
815 interrupts = <0 160 0x4>;
820 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
821 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
823 interrupts = <0 118 0x4>, /* controller interrupt */
824 <0 117 0x4>; /* PME interrupt */
831 bus-range = <0x0 0xff>;
832 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
833 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
836 interrupt-map-mask = <0 0 0 7>;
837 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
838 <0000 0 0 2 &gic 0 111 0x4>,
839 <0000 0 0 3 &gic 0 112 0x4>,
840 <0000 0 0 4 &gic 0 113 0x4>;
846 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
847 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
849 interrupts = <0 128 0x4>,
850 <0 127 0x4>;
857 bus-range = <0x0 0xff>;
858 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
859 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
862 interrupt-map-mask = <0 0 0 7>;
863 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
864 <0000 0 0 2 &gic 0 121 0x4>,
865 <0000 0 0 3 &gic 0 122 0x4>,
866 <0000 0 0 4 &gic 0 123 0x4>;
872 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
873 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
875 interrupts = <0 162 0x4>,
876 <0 161 0x4>;
883 bus-range = <0x0 0xff>;
884 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
885 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
888 interrupt-map-mask = <0 0 0 7>;
889 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
890 <0000 0 0 2 &gic 0 155 0x4>,
891 <0000 0 0 3 &gic 0 156 0x4>,
892 <0000 0 0 4 &gic 0 157 0x4>;
898 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
899 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
900 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
910 block-offset = <0x10000>;
919 reg = <0x0 0x1ee2140 0x0 0x4>;
925 reg = <0x0 0x29d0000 0x0 0x10000>;
926 fsl,rcpm-wakeup = <&rcpm 0x20000>;