Lines Matching +full:2 +full:c010000
17 #address-cells = <2>;
18 #size-cells = <2>;
36 #cooling-cells = <2>;
47 #cooling-cells = <2>;
102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
104 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
119 #address-cells = <2>;
120 #size-cells = <2>;
188 #address-cells = <2>;
189 #size-cells = <2>;
220 #clock-cells = <2>;
312 clocks = <&clockgen 2 0>, <&clockgen 2 0>;
355 dmas = <&edma0 0 54>, <&edma0 0 2>;
367 clocks = <&clockgen 2 1>;
380 clocks = <&clockgen 2 1>;
497 #dma-cells = <2>;
516 #gpio-cells = <2>;
518 #interrupt-cells = <2>;
527 #gpio-cells = <2>;
529 #interrupt-cells = <2>;
538 #gpio-cells = <2>;
540 #interrupt-cells = <2>;
583 #size-cells = <2>;
594 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
610 #size-cells = <2>;
621 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
734 fsl,dma-queues = <2>;
746 cluster1_core1_watchdog: watchdog@c010000 {
899 #size-cells = <2>;
933 enetc_port2: ethernet@0,2 {
955 clocks = <&clockgen 2 3>;
981 mscc_felix_port2: port@2 {
982 reg = <2>;
1050 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
1051 <&clockgen 2 2>;