Kconfig - OpenGrok cross reference for /OK3568_Linux_fs/kernel/arch/arm64/Kconfig

382 	  The workaround promotes data cache clean instructions to
384 	  Please note that this does not necessarily enable the workaround,
404 	  The workaround promotes data cache clean instructions to
406 	  Please note that this does not necessarily enable the workaround,
427 	  The workaround promotes data cache clean instructions to
430 	  workaround, as it depends on the alternative framework, which will
449 	  The workaround promotes data cache clean instructions to
451 	  Please note that this does not necessarily enable the workaround,
467 	  The workaround is to promote device loads to use Load-Acquire
469 	  Please note that this does not necessarily enable the workaround,
488 	  The workaround is to verify that the Stage 1 translation
490 	  Please note that this does not necessarily enable the workaround,
502 	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
525 	  The workaround is to write the contextidr_el1 register on exception
527 	  Please note that this does not necessarily enable the workaround,
549 	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
553 	  without a break-before-make. The workaround is to disable the usage
564 	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
581 	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
607 	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
623 	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
632 	  workaround repeats the TLBI+DSB operation.
638 	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
653 	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
656 	  This option adds a workaround for ARM Neoverse-N1 erratum
660 	  modified by another CPU. The workaround depends on a firmware
663 	  Workaround the issue by hiding the DIC feature from EL0. This
669 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
672 	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
676 	  non-cacheable memory attributes. The workaround depends on a firmware
679 	  KVM guests must also have the workaround implemented or they can
692 	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
694 	  hardware update of the page table's dirty bit. The workaround
703 	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
707 	  Enable workaround for ARM Cortex-A710 erratum 2054223
713 	  Workaround is to issue two TSB consecutively on affected cores.
718 	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
722 	  Enable workaround for ARM Neoverse-N2 erratum 2067961
728 	  Workaround is to issue two TSB consecutively on affected cores.
737 	  This option adds the workaround for ARM Cortex-A510 erratum 2454944.
746 	  The workaround is to enforce as far as reasonably possible that all
750 	  the workaround, lazy TLB flushing should be disabled.
756 	bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
760 	  This option adds the workaround for ARM Cortex-A510 erratum 2457168.
777 	  Enable workaround for errata 22375 and 24313.
852 	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
862 	  The workaround is to ensure these bits are clear in TCR_ELx.
863 	  The workaround only affects the Fujitsu-A64FX.
920 	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1880 	  Specific errata workaround(s) might also force module PLTs to be