Kconfig - OpenGrok cross reference for /OK3568_Linux_fs/kernel/arch/arm64/Kconfig

1 # SPDX-License-Identifier: GPL-2.0-only
168 		if $(cc-option,-fpatchable-function-entry=2)
217 	  ARM 64-bit (AArch64) Linux support.
249 #  VA_BITS - PAGE_SHIFT - 3
342 	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
369 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
374 	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
377 	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
383 	  data cache clean-and-invalidate.
391 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
396 	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
405 	  data cache clean-and-invalidate.
413 	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
418 	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
421 	  If a Cortex-A53 processor is executing a store or prefetch for
428 	  data cache clean-and-invalidate.
436 	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
441 	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
450 	  data cache clean-and-invalidate.
458 	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
462 	  erratum 832075 on Cortex-A57 parts up to r1p2.
464 	  Affected Cortex-A57 parts might deadlock when exclusive load/store
465 	  instructions to Write-Back memory are mixed with Device loads.
467 	  The workaround is to promote device loads to use Load-Acquire
476 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
481 	  erratum 834220 on Cortex-A57 parts up to r1p2.
483 	  Affected Cortex-A57 parts might report a Stage 2 translation
497 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
501 	  This option removes the AES hwcap for aarch32 user-space to
502 	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
513 	bool "Cortex-A53: 845719: a load might read incorrect data"
518 	  erratum 845719 on Cortex-A53 parts up to r0p4.
520 	  When running a compat (AArch32) userspace on an affected Cortex-A53
526 	  return to a 32-bit task.
534 	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
538 	  This option links the kernel with '--fix-cortex-a53-843419' and
541 	  Cortex-A53 parts up to r0p4.
546 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
549 	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
551 	  Affected Cortex-A55 cores (all revisions) could cause incorrect
553 	  without a break-before-make. The workaround is to disable the usage
560 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
564 	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
567 	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
577 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
581 	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
583 	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
590 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
594 	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
597 	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
603 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
607 	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
609 	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
619 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
623 	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
625 	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
629 	  break-before-make sequence, then under very rare circumstances
635 	bool "Cortex-A76: Software Step might prevent interrupt recognition"
638 	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
640 	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
653 	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
656 	  This option adds a workaround for ARM Neoverse-N1 erratum
659 	  Affected Neoverse-N1 cores could execute a stale instruction when
664 	  forces user-space to perform cache maintenance.
669 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
672 	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
674 	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
675 	  of a store-exclusive or read of PAR_EL1 and a load with device or
676 	  non-cacheable memory attributes. The workaround depends on a firmware
689 	bool "Cortex-A510: 2051678: disable Hardware Update of the page table's dirty bit"
692 	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
693 	  Affected Coretex-A510 might not respect the ordering rules for
703 	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
707 	  Enable workaround for ARM Cortex-A710 erratum 2054223
718 	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
722 	  Enable workaround for ARM Neoverse-N2 erratum 2067961
733 	bool "Cortex-A510: 2454944: Unmodified cache line might be written back to memory"
737 	  This option adds the workaround for ARM Cortex-A510 erratum 2454944.
739 	  Affected Cortex-A510 core might write unmodified cache lines back to
741 	  management for non-coherent DMA relies. If a cache line is
742 	  speculatively fetched while a non-coherent device is writing directly
747 	  non-coherent DMA transfers are bounced and/or remapped to minimise
756 	bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
760 	  This option adds the workaround for ARM Cortex-A510 erratum 2457168.
763 	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
779 	  This implements two gicv3-its errata workarounds for ThunderX. Both
815 	  contains data for a non-current ASID.  The fix is to
826 	  interrupts in host. Trapping both GICv3 group-0 and group-1
849 	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
852 	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
853 	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
857 	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
858 	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
859 	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
860 	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
863 	  The workaround only affects the Fujitsu-A64FX.
914 	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
915 	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
920 	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
924 	  MSI doorbell writes with non-zero values for the device ID.
954 	  look-up. AArch32 emulation requires applications compiled
970 	bool "36-bit" if EXPERT
974 	bool "39-bit"
978 	bool "42-bit"
982 	bool "47-bit"
986 	bool "48-bit"
989 	bool "52-bit"
992 	  Enable 52-bit virtual addressing for userspace when explicitly
993 	  requested via a hint to mmap(). The kernel will also use 52-bit
995 	  this feature is available, otherwise it reverts to 48-bit).
997 	  NOTE: Enabling 52-bit virtual addressing in conjunction with
1000 	  impact on its susceptibility to brute-force attacks.
1002 	  If unsure, select 48-bit virtual addressing instead.
1007 	bool "Force 52-bit virtual addresses for userspace"
1010 	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
1011 	  to maintain compatibility with older software by providing 48-bit VAs
1014 	  This configuration option disables the 48-bit compatibility logic, and
1015 	  forces all userspace addresses to be 52-bit on HW that supports it. One
1036 	bool "48-bit"
1039 	bool "52-bit (ARMv8.2)"
1043 	  Enable support for a 52-bit physical address space, introduced as
1044 	  part of the ARMv8.2-LPA extension.
1047 	  do not support ARMv8.2-LPA, but with some added memory overhead (and
1066 	bool "Build big-endian kernel"
1069 	  Say Y if you plan on running a kernel with a big-endian userspace.
1072 	bool "Build little-endian kernel"
1074 	  Say Y if you plan on running a kernel with a little-endian userspace.
1080 	bool "Multi-core scheduler support"
1082 	  Multi-core scheduler support improves the CPU scheduler's decision
1083 	  making when dealing with multi-core CPU chips at a cost of slightly
1094 	int "Maximum number of CPUs (2-4096)"
1099 	bool "Support for hot-pluggable CPUs"
1111 	  Enable NUMA (Non-Uniform Memory Access) support.
1179 	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1247 	  loaded in the main kernel with kexec-tools into a specially
1251 	  For more details see Documentation/admin-guide/kdump/kdump.rst
1283 		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1286 	  4M allocations matching the default size used by generic code.
1292 	  Speculation attacks against some high-performance processors can
1304 	  Speculation attacks against some high-performance processors can
1306 	  When taking an exception from user-space, a sequence of branches
1313 	  Apply read-only attributes of VM areas to the linear alias of
1314 	  the backing pages as well. This prevents code or read-only data
1327 	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1338 	  Documentation/arm64/tagged-address-abi.rst.
1341 	bool "Kernel support for 32-bit EL0"
1348 	  This option enables support for a 32-bit EL0 running under a 64-bit
1349 	  kernel at EL1. AArch32-specific components such as system calls,
1357 	  If you want to execute 32-bit userspace applications, say Y.
1362 	bool "Enable kuser helpers page for 32-bit applications"
1365 	  Warning: disabling this option may break 32-bit user programs.
1389 	bool "Enable vDSO for 32-bit applications"
1395 	  Place in the process address space of 32-bit applications an
1399 	  You must have a 32-bit build of glibc 2.22 or later for programs
1403 	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1407 	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1408 	  otherwise with '-marm'.
1450 	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1451 	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1466 	  The SETEND instruction alters the data-endianness of the
1474 	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1475 	  endian - is hotplugged in after this feature has been enabled, there could
1494 	  Similarly, writes to read-only pages with the DBM bit set will
1495 	  clear the read-only bit (AP[2]) instead of raising a
1499 	  to work on pre-ARMv8.1 hardware and the performance impact is
1507 	 prevents the kernel or hypervisor from accessing user-space (EL0)
1517 	def_bool $(as-instr,.arch_extension rcpc)
1520 	def_bool $(as-instr,.arch_extension lse)
1536 	  Say Y here to make use of these instructions for the in-kernel
1568 	  variant of the load/store instructions. This ensures that user-space
1573 	  Choosing this option will cause copy_to_user() et al to use user-space
1644 	  context-switched along with the process.
1646 	  If the compiler supports the -mbranch-protection or
1647 	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1668 	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1672 	def_bool $(cc-option,-msign-return-address=all)
1675 	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1678 	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1708 	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1715 	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1726 	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1771 	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1795 	# ".arch armv8.5-a+memtag" below. However, this was incomplete
1799 	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1812 	  architectural support for run-time, always-on detection of
1814 	  to eliminate vulnerabilities arising from memory-unsafe
1822 	  not be allowed a late bring-up.
1828 	  Documentation/arm64/memory-tagging-extension.rst.
1857 	  If you need the kernel to boot on SVE-capable hardware with broken
1884 	bool "Support for NMI-like interrupts"
1887 	  Adds support for mimicking Non-Maskable Interrupts through the use of
1931 	  random u64 value in /chosen/kaslr-seed at kernel entry.
1956 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
1979 	  Provide a set of default command-line options at build time by
1993 	  Uses the command-line options passed by the boot loader. If
2000 	  The command-line arguments provided by the boot loader will be
2009 	  command-line options your boot loader passes to the kernel.
2030 	  by UEFI firmware (such as non-volatile variables, realtime
2044 	  continue to boot on existing non-UEFI platforms.