Lines Matching +full:0 +full:x4a000000
36 #define S3C_IRQTYPE_NONE 0
72 * [0] ... main_intc
155 return 0; in s3c_irq_type()
164 unsigned long newvalue = 0, value; in s3c_irqext_type_set()
168 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); in s3c_irqext_type_set()
207 return 0; in s3c_irqext_type_set()
306 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0; in s3c_irq_demux()
338 intc_offset = 0; in s3c24xx_handle_intc()
367 * s3c_intc[0] = s3c24xx_init_intc() in s3c24xx_handle_irq()
372 * setting s3c_intc[0] only if it was called with num_ctrl=0. There is no in s3c24xx_handle_irq()
373 * such code path, so again the s3c_intc[0] will have a valid pointer if in s3c24xx_handle_irq()
376 * Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something. in s3c24xx_handle_irq()
378 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) in s3c24xx_handle_irq()
411 return 0; in s3c24xx_set_fiq()
415 intmod = 0; in s3c24xx_set_fiq()
446 return 0; in s3c24xx_irq_map()
503 return 0; in s3c24xx_irq_map()
521 last = 0; in s3c24xx_clear_intc()
522 for (i = 0; i < 4; i++) { in s3c24xx_clear_intc()
525 if (pend == 0 || pend == last) in s3c24xx_clear_intc()
543 void __iomem *base = (void *)0xf6000000; /* static mapping */ in s3c24xx_init_intc()
562 case 0x4a000000: in s3c24xx_init_intc()
565 intc->reg_mask = base + 0x08; in s3c24xx_init_intc()
566 intc->reg_intpnd = base + 0x10; in s3c24xx_init_intc()
568 irq_start = S3C2410_IRQ(0); in s3c24xx_init_intc()
570 case 0x4a000018: in s3c24xx_init_intc()
572 intc->reg_pending = base + 0x18; in s3c24xx_init_intc()
573 intc->reg_mask = base + 0x1c; in s3c24xx_init_intc()
575 irq_start = S3C2410_IRQSUB(0); in s3c24xx_init_intc()
577 case 0x4a000040: in s3c24xx_init_intc()
579 intc->reg_pending = base + 0x40; in s3c24xx_init_intc()
580 intc->reg_mask = base + 0x48; in s3c24xx_init_intc()
581 intc->reg_intpnd = base + 0x50; in s3c24xx_init_intc()
583 irq_start = S3C2416_IRQ(0); in s3c24xx_init_intc()
585 case 0x560000a4: in s3c24xx_init_intc()
587 base = (void *)0xfd000000; in s3c24xx_init_intc()
589 intc->reg_mask = base + 0xa4; in s3c24xx_init_intc()
590 intc->reg_pending = base + 0xa8; in s3c24xx_init_intc()
603 0, &s3c24xx_irq_ops, in s3c24xx_init_intc()
703 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL, in s3c2410_init_irq()
704 0x4a000000); in s3c2410_init_irq()
705 if (IS_ERR(s3c_intc[0])) { in s3c2410_init_irq()
710 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0], in s3c2410_init_irq()
711 s3c_intc[0], 0x4a000018); in s3c2410_init_irq()
712 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); in s3c2410_init_irq()
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
805 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, in s3c2412_init_irq()
806 0x4a000000); in s3c2412_init_irq()
807 if (IS_ERR(s3c_intc[0])) { in s3c2412_init_irq()
812 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4); in s3c2412_init_irq()
813 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0], in s3c2412_init_irq()
814 s3c_intc[0], 0x4a000018); in s3c2412_init_irq()
904 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, in s3c2416_init_irq()
905 0x4a000000); in s3c2416_init_irq()
906 if (IS_ERR(s3c_intc[0])) { in s3c2416_init_irq()
911 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); in s3c2416_init_irq()
912 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0], in s3c2416_init_irq()
913 s3c_intc[0], 0x4a000018); in s3c2416_init_irq()
915 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0], in s3c2416_init_irq()
916 NULL, 0x4a000040); in s3c2416_init_irq()
983 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, in s3c2440_init_irq()
984 0x4a000000); in s3c2440_init_irq()
985 if (IS_ERR(s3c_intc[0])) { in s3c2440_init_irq()
990 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); in s3c2440_init_irq()
991 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0], in s3c2440_init_irq()
992 s3c_intc[0], 0x4a000018); in s3c2440_init_irq()
1056 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, in s3c2442_init_irq()
1057 0x4a000000); in s3c2442_init_irq()
1058 if (IS_ERR(s3c_intc[0])) { in s3c2442_init_irq()
1063 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); in s3c2442_init_irq()
1064 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0], in s3c2442_init_irq()
1065 s3c_intc[0], 0x4a000018); in s3c2442_init_irq()
1146 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, in s3c2443_init_irq()
1147 0x4a000000); in s3c2443_init_irq()
1148 if (IS_ERR(s3c_intc[0])) { in s3c2443_init_irq()
1153 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); in s3c2443_init_irq()
1154 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0], in s3c2443_init_irq()
1155 s3c_intc[0], 0x4a000018); in s3c2443_init_irq()
1181 return 0; in s3c24xx_irq_map_of()
1200 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) { in s3c24xx_irq_xlate_of()
1201 pr_err("controller number %d invalid\n", intspec[0]); in s3c24xx_irq_xlate_of()
1204 intc = s3c_intc[intspec[0]]; in s3c24xx_irq_xlate_of()
1206 *out_hwirq = intspec[0] * 32 + intspec[2]; in s3c24xx_irq_xlate_of()
1217 /* parent_intc is always s3c_intc[0], so no offset */ in s3c24xx_irq_xlate_of()
1219 if (irqno < 0) { in s3c24xx_irq_xlate_of()
1227 return 0; in s3c24xx_irq_xlate_of()
1253 reg_base = of_iomap(np, 0); in s3c_init_intc_of()
1266 for (i = 0; i < num_ctrl; i++) { in s3c_init_intc_of()
1285 intc->reg_mask = reg_base + ctrl->offset + 0x4; in s3c_init_intc_of()
1298 intc->reg_mask = reg_base + ctrl->offset + 0x08; in s3c_init_intc_of()
1299 intc->reg_intpnd = reg_base + ctrl->offset + 0x10; in s3c_init_intc_of()
1308 return 0; in s3c_init_intc_of()
1314 .offset = 0,
1317 .offset = 0x18,
1318 .parent = &s3c_intc[0],
1333 .offset = 0,
1336 .offset = 0x18,
1337 .parent = &s3c_intc[0],
1340 .offset = 0x40,