Lines Matching refs:writel_relaxed
318 writel_relaxed(byte, uartdbg_base + 0x0); in uart_wrtie_byte()
420 writel_relaxed(0xffff0000, cru_base + RV1106_CRU_GATE_CON(i)); in clock_suspend()
426 writel_relaxed(0xffff0000, pmucru_base + RV1106_PMUCRU_GATE_CON(i)); in clock_suspend()
432 writel_relaxed(0xffff0000, pericru_base + RV1106_PERICRU_GATE_CON(i)); in clock_suspend()
438 writel_relaxed(0xffff0000, npucru_base + RV1106_NPUCRU_GATE_CON(i)); in clock_suspend()
444 writel_relaxed(0xffff0000, venccru_base + RV1106_VENCCRU_GATE_CON(i)); in clock_suspend()
450 writel_relaxed(0xffff0000, vicru_base + RV1106_VICRU_GATE_CON(i)); in clock_suspend()
456 writel_relaxed(0xffff0000, vocru_base + RV1106_VOCRU_GATE_CON(i)); in clock_suspend()
465 writel_relaxed(WITH_16BITS_WMSK(ddr_data.cru_gate_con[i]), in clock_resume()
469 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmucru_gate_con[i]), in clock_resume()
473 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pericru_gate_con[i]), in clock_resume()
477 writel_relaxed(WITH_16BITS_WMSK(ddr_data.npucru_gate_con[i]), in clock_resume()
481 writel_relaxed(WITH_16BITS_WMSK(ddr_data.venccru_gate_con[i]), in clock_resume()
485 writel_relaxed(WITH_16BITS_WMSK(ddr_data.vicru_gate_con[i]), in clock_resume()
489 writel_relaxed(WITH_16BITS_WMSK(ddr_data.vocru_gate_con[i]), in clock_resume()
503 writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 6), vigrf_base + 0x0); in pvtm_32k_config()
504 writel_relaxed(BITS_WITH_WMASK(0x4, 0xf, 0), ioc_base[0] + 0); in pvtm_32k_config()
505 writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 15), in pvtm_32k_config()
507 writel_relaxed(BITS_WITH_WMASK(0x1, 0x3, 0), in pvtm_32k_config()
510 writel_relaxed(BITS_WITH_WMASK(0, 0x3, 0), in pvtm_32k_config()
512 writel_relaxed(RV1106_PVTM_CALC_CNT, in pvtm_32k_config()
514 writel_relaxed(BITS_WITH_WMASK(0, 0x3, PVTM_START), in pvtm_32k_config()
518 writel_relaxed(BITS_WITH_WMASK(0, 0x7, PVTM_OSC_SEL), in pvtm_32k_config()
520 writel_relaxed(BITS_WITH_WMASK(1, 0x1, PVTM_OSC_EN), in pvtm_32k_config()
522 writel_relaxed(BITS_WITH_WMASK(1, 0x1, PVTM_RND_SEED_EN), in pvtm_32k_config()
526 writel_relaxed(BITS_WITH_WMASK(1, 0x1, PVTM_START), in pvtm_32k_config()
544 writel_relaxed(WITH_16BITS_WMSK(pvtm_div), in pvtm_32k_config()
548 writel_relaxed(BITS_WITH_WMASK(0x2, 0x3, 0), in pvtm_32k_config()
561 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmucru_sel_con7), in pvtm_32k_config_restore()
577 writel_relaxed(val & ~(BIT(0) | BIT(1)), ddrc_base + 0x30); in ddr_sleep_config()
580 writel_relaxed(BITS_WITH_WMASK(0x12, 0x1f, 0), ddrgrf_base + RV1106_DDRGRF_CON(1)); in ddr_sleep_config()
582 writel_relaxed(BITS_WITH_WMASK(0x3ff, 0x3ff, 0), ddrgrf_base + RV1106_DDRGRF_CON(2)); in ddr_sleep_config()
585 writel_relaxed(BITS_WITH_WMASK(0x3, 0x3, 8), ddrgrf_base + RV1106_DDRGRF_CON(3)); in ddr_sleep_config()
592 writel_relaxed(val, ddrc_base + 0x198); in ddr_sleep_config()
595 writel_relaxed(val, ddrc_base + 0x198); in ddr_sleep_config()
598 writel_relaxed(BITS_WITH_WMASK(0x0, 0x7, 9), pmugrf_base + RV1106_PMUGRF_SOC_CON(0)); in ddr_sleep_config()
603 writel_relaxed(WITH_16BITS_WMSK(ddr_data.ddrgrf_con3), in ddr_sleep_config_restore()
690 writel_relaxed(BITS_WITH_WMASK(0x4, 0x7, 0), pmugrf_base + RV1106_PMUGRF_SOC_CON(1)); in pmu_sleep_config()
692 writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 0), pmugrf_base + RV1106_PMUGRF_SOC_CON(1)); in pmu_sleep_config()
694 writel_relaxed(BITS_WITH_WMASK(0x1, 0xf, 12), ioc_base[0] + 0); in pmu_sleep_config()
697 writel_relaxed(0xffffff01, pmu_base + RV1106_PMU_INFO_TX_CON); in pmu_sleep_config()
698 writel_relaxed(BITS_WITH_WMASK(0x1, 0xf, 4), ioc_base[1] + 0); in pmu_sleep_config()
701 writel_relaxed(clk_freq_khz * 32, pmu_base + RV1106_PMU_OSC_STABLE_CNT); in pmu_sleep_config()
702 writel_relaxed(clk_freq_khz * 32, pmu_base + RV1106_PMU_PMIC_STABLE_CNT); in pmu_sleep_config()
703 writel_relaxed(clk_freq_khz * 3000, pmu_base + RV1106_PMU_WAKEUP_TIMEOUT_CNT); in pmu_sleep_config()
709 writel_relaxed(24000 * 2, pmu_base + RV1106_PMU_WAKEUP_RSTCLR_CNT); in pmu_sleep_config()
710 writel_relaxed(24000 * 5, pmu_base + RV1106_PMU_PLL_LOCK_CNT); in pmu_sleep_config()
711 writel_relaxed(24000 * 5, pmu_base + RV1106_PMU_PWM_SWITCH_CNT); in pmu_sleep_config()
714 writel_relaxed(0xffffffff, pmugrf_base + RV1106_PMUGRF_SOC_CON(4)); in pmu_sleep_config()
715 writel_relaxed(0xffffff47, pmugrf_base + RV1106_PMUGRF_SOC_CON(5)); in pmu_sleep_config()
717 writel_relaxed(0x00010001, pmu_base + RV1106_PMU_INT_MASK_CON); in pmu_sleep_config()
718 writel_relaxed(WITH_16BITS_WMSK(pmu_scu_con), pmu_base + RV1106_PMU_SCU_PWR_CON); in pmu_sleep_config()
720 writel_relaxed(WITH_16BITS_WMSK(pmu_cru_con[0]), pmu_base + RV1106_PMU_CRU_PWR_CON0); in pmu_sleep_config()
721 writel_relaxed(WITH_16BITS_WMSK(pmu_cru_con[1]), pmu_base + RV1106_PMU_CRU_PWR_CON1); in pmu_sleep_config()
722 writel_relaxed(WITH_16BITS_WMSK(pmu_bus_idle_con), pmu_base + RV1106_PMU_BIU_IDLE_CON); in pmu_sleep_config()
724 writel_relaxed(WITH_16BITS_WMSK(pmu_ddr_con), pmu_base + RV1106_PMU_DDR_PWR_CON); in pmu_sleep_config()
725 writel_relaxed(WITH_16BITS_WMSK(pmu_pll_con), pmu_base + RV1106_PMU_PLLPD_CON); in pmu_sleep_config()
726 writel_relaxed(pmu_wkup_con, pmu_base + RV1106_PMU_WAKEUP_INT_CON); in pmu_sleep_config()
727 writel_relaxed(WITH_16BITS_WMSK(pmu_pwr_con), pmu_base + RV1106_PMU_PWR_CON); in pmu_sleep_config()
730 writel_relaxed(0, pmugrf_base + RV1106_PMUGRF_OS_REG(9)); in pmu_sleep_config()
732 writel_relaxed(0, pmugrf_base + RV1106_PMUGRF_OS_REG(10)); in pmu_sleep_config()
734 writel_relaxed(PMU_SUSPEND_MAGIC, pmugrf_base + RV1106_PMUGRF_OS_REG(9)); in pmu_sleep_config()
743 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_INFO_TX_CON); in pmu_sleep_restore()
744 writel_relaxed(0x00010000, pmu_base + RV1106_PMU_INT_MASK_CON); in pmu_sleep_restore()
745 writel_relaxed(0x00000000, pmu_base + RV1106_PMU_WAKEUP_INT_CON); in pmu_sleep_restore()
746 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_PWR_CON); in pmu_sleep_restore()
747 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_BIU_IDLE_CON); in pmu_sleep_restore()
748 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_DDR_PWR_CON); in pmu_sleep_restore()
749 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_SCU_PWR_CON); in pmu_sleep_restore()
750 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_PLLPD_CON); in pmu_sleep_restore()
751 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_CRU_PWR_CON0); in pmu_sleep_restore()
752 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_CRU_PWR_CON1); in pmu_sleep_restore()
754 writel_relaxed(WITH_16BITS_WMSK(ddr_data.ioc1_1a_iomux_l), in pmu_sleep_restore()
756 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con1), in pmu_sleep_restore()
758 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con4), in pmu_sleep_restore()
760 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con5), in pmu_sleep_restore()
793 writel_relaxed(WITH_16BITS_WMSK(ddr_data.ioc0_1a_iomux_l), in soc_sleep_restore()
810 writel_relaxed(BITS_WITH_WMASK(func, 0xf, sft), ioc_base[0] + 0); in gpio0_set_iomux()
812 writel_relaxed(BITS_WITH_WMASK(func, 0xf, sft), ioc_base[0] + 4); in gpio0_set_iomux()
819 writel_relaxed(BITS_WITH_WMASK(pull, 0x3, sft), ioc_base[0] + 0x38); in gpio0_set_pull()
827 writel_relaxed(BITS_WITH_WMASK(out, 0x1, sft), in gpio0_set_direct()
830 writel_relaxed(BITS_WITH_WMASK(out, 0x1, sft), in gpio0_set_direct()
879 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l), ioc_base[0] + 0); in gpio_restore()
880 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h), ioc_base[0] + 0x4); in gpio_restore()
882 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a0_pull), ioc_base[0] + 0x38); in gpio_restore()
884 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0_ddr_l), in gpio_restore()
886 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0_ddr_h), in gpio_restore()
916 writel_relaxed(0x003f0000, cru_base + 0x280); in vd_log_regs_restore()
927 writel_relaxed(WITH_16BITS_WMSK(cru_mode), cru_base + 0x280); in vd_log_regs_restore()
1088 writel_relaxed(BITS_WITH_WMASK(1, 0x1, 10), pmusgrf_base + RV1106_PMUSGRF_SOC_CON(1)); in rv1106_suspend_init()
1090 writel_relaxed(BITS_WITH_WMASK(0, 0x1, 10), pmusgrf_base + RV1106_PMUSGRF_SOC_CON(1)); in rv1106_suspend_init()
1093 writel_relaxed(0x07ff07ff, pmu_base + RV1106_PMU_BIU_AUTO_CON); in rv1106_suspend_init()