283 	if (readl_relaxed(cru_base + RV1106_CRU_PLL_CON(pll_id, 1)) & CRU_PLLCON1_PWRDOWN)  in pm_pll_wait_lock()
287 		if (readl_relaxed(cru_base + RV1106_CRU_PLL_CON(pll_id, 1)) &  in pm_pll_wait_lock()
320 	while (!(readl_relaxed(uartdbg_base + 0x14) & 0x40))  in uart_wrtie_byte()
337 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_EN_L));	\
339 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_EN_H));	\
341 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_MASK_L));	\
343 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_MASK_H));	\
345 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_STATUS));	\
347 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_RAWSTATUS));\
419 			readl_relaxed(cru_base + RV1106_CRU_GATE_CON(i));  in clock_suspend()
425 			readl_relaxed(pmucru_base + RV1106_PMUCRU_GATE_CON(i));  in clock_suspend()
431 			readl_relaxed(pericru_base + RV1106_PERICRU_GATE_CON(i));  in clock_suspend()
437 			readl_relaxed(npucru_base + RV1106_NPUCRU_GATE_CON(i));  in clock_suspend()
443 			readl_relaxed(venccru_base + RV1106_VENCCRU_GATE_CON(i));  in clock_suspend()
449 			readl_relaxed(vicru_base + RV1106_VICRU_GATE_CON(i));  in clock_suspend()
455 			readl_relaxed(vocru_base + RV1106_VOCRU_GATE_CON(i));  in clock_suspend()
500 		readl_relaxed(pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));  in pvtm_32k_config()
530 		while (readl_relaxed(pmupvtm_base + RV1106_PVTM_STATUS(1)) < 30)  in pvtm_32k_config()
535 		while (!readl_relaxed(pmupvtm_base + RV1106_PVTM_STATUS(0)) & 0x1)  in pvtm_32k_config()
538 		value = (readl_relaxed(pmupvtm_base + RV1106_PVTM_STATUS(1)));  in pvtm_32k_config()
569 	ddr_data.ddrc_pwrctrl = readl_relaxed(ddrc_base + 0x30);  in ddr_sleep_config()
570 	ddr_data.ddrgrf_con1 = readl_relaxed(ddrgrf_base + RV1106_DDRGRF_CON(1));  in ddr_sleep_config()
571 	ddr_data.ddrgrf_con2 = readl_relaxed(ddrgrf_base + RV1106_DDRGRF_CON(2));  in ddr_sleep_config()
572 	ddr_data.ddrgrf_con3 = readl_relaxed(ddrgrf_base + RV1106_DDRGRF_CON(3));  in ddr_sleep_config()
573 	ddr_data.ddrc_dfilpcfg0 = readl_relaxed(ddrc_base + 0x198);  in ddr_sleep_config()
574 	ddr_data.pmugrf_soc_con0 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(0));  in ddr_sleep_config()
576 	val = readl_relaxed(ddrc_base + 0x30);  in ddr_sleep_config()
587 	while ((readl_relaxed(ddrc_base + 0x4) & 0x7) != 0x1)  in ddr_sleep_config()
590 	val = readl_relaxed(ddrc_base + 0x198) & ~(0xf << 12 | 0xf << 4);  in ddr_sleep_config()
594 	val = readl_relaxed(ddrc_base + 0x198) | BIT(8) | BIT(0);  in ddr_sleep_config()
613 	ddr_data.pmugrf_soc_con1 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(1));  in pmu_sleep_config()
614 	ddr_data.pmugrf_soc_con4 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(4));  in pmu_sleep_config()
615 	ddr_data.pmugrf_soc_con5 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(5));  in pmu_sleep_config()
616 	ddr_data.ioc1_1a_iomux_l = readl_relaxed(ioc_base[1] + 0);  in pmu_sleep_config()
740 	ddr_data.pmu_wkup_int_st = readl_relaxed(pmu_base + RV1106_PMU_WAKEUP_INT_ST);  in pmu_sleep_restore()
741 	ddr_data.gpio0_int_st = readl_relaxed(gpio_base[0] + RV1106_GPIO_INT_STATUS);  in pmu_sleep_restore()
766 	ddr_data.ioc0_1a_iomux_l = readl_relaxed(ioc_base[0] + 0);  in soc_sleep_config()
836 	ddr_data.gpio0a_iomux_l = readl_relaxed(ioc_base[0] + 0);  in gpio_config()
837 	ddr_data.gpio0a_iomux_h = readl_relaxed(ioc_base[0] + 0x4);  in gpio_config()
838 	ddr_data.gpio0a0_pull = readl_relaxed(ioc_base[0] + 0x38);  in gpio_config()
839 	ddr_data.gpio0_ddr_l = readl_relaxed(gpio_base[0] + RV1106_GPIO_SWPORT_DDR_L);  in gpio_config()
840 	ddr_data.gpio0_ddr_h = readl_relaxed(gpio_base[0] + RV1106_GPIO_SWPORT_DDR_H);  in gpio_config()
895 	cru_mode = readl_relaxed(cru_base + 0x280);  in vd_log_regs_save()