86 static void __iomem *pmu_base;  variable
91 static void __iomem *pmu_base;  variable
697 	writel_relaxed(0xffffff01, pmu_base + RV1106_PMU_INFO_TX_CON);  in pmu_sleep_config()
701 	writel_relaxed(clk_freq_khz * 32, pmu_base + RV1106_PMU_OSC_STABLE_CNT);  in pmu_sleep_config()
702 	writel_relaxed(clk_freq_khz * 32, pmu_base + RV1106_PMU_PMIC_STABLE_CNT);  in pmu_sleep_config()
703 	writel_relaxed(clk_freq_khz * 3000, pmu_base + RV1106_PMU_WAKEUP_TIMEOUT_CNT);  in pmu_sleep_config()
709 	writel_relaxed(24000 * 2, pmu_base + RV1106_PMU_WAKEUP_RSTCLR_CNT);  in pmu_sleep_config()
710 	writel_relaxed(24000 * 5, pmu_base + RV1106_PMU_PLL_LOCK_CNT);  in pmu_sleep_config()
711 	writel_relaxed(24000 * 5, pmu_base + RV1106_PMU_PWM_SWITCH_CNT);  in pmu_sleep_config()
717 	writel_relaxed(0x00010001, pmu_base + RV1106_PMU_INT_MASK_CON);  in pmu_sleep_config()
718 	writel_relaxed(WITH_16BITS_WMSK(pmu_scu_con), pmu_base + RV1106_PMU_SCU_PWR_CON);  in pmu_sleep_config()
720 	writel_relaxed(WITH_16BITS_WMSK(pmu_cru_con[0]), pmu_base + RV1106_PMU_CRU_PWR_CON0);  in pmu_sleep_config()
721 	writel_relaxed(WITH_16BITS_WMSK(pmu_cru_con[1]), pmu_base + RV1106_PMU_CRU_PWR_CON1);  in pmu_sleep_config()
722 	writel_relaxed(WITH_16BITS_WMSK(pmu_bus_idle_con), pmu_base + RV1106_PMU_BIU_IDLE_CON);  in pmu_sleep_config()
724 	writel_relaxed(WITH_16BITS_WMSK(pmu_ddr_con), pmu_base + RV1106_PMU_DDR_PWR_CON);  in pmu_sleep_config()
725 	writel_relaxed(WITH_16BITS_WMSK(pmu_pll_con), pmu_base + RV1106_PMU_PLLPD_CON);  in pmu_sleep_config()
726 	writel_relaxed(pmu_wkup_con, pmu_base + RV1106_PMU_WAKEUP_INT_CON);  in pmu_sleep_config()
727 	writel_relaxed(WITH_16BITS_WMSK(pmu_pwr_con), pmu_base + RV1106_PMU_PWR_CON);  in pmu_sleep_config()
740 	ddr_data.pmu_wkup_int_st = readl_relaxed(pmu_base + RV1106_PMU_WAKEUP_INT_ST);  in pmu_sleep_restore()
743 	writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_INFO_TX_CON);  in pmu_sleep_restore()
744 	writel_relaxed(0x00010000, pmu_base + RV1106_PMU_INT_MASK_CON);  in pmu_sleep_restore()
745 	writel_relaxed(0x00000000, pmu_base + RV1106_PMU_WAKEUP_INT_CON);  in pmu_sleep_restore()
746 	writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_PWR_CON);  in pmu_sleep_restore()
747 	writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_BIU_IDLE_CON);  in pmu_sleep_restore()
748 	writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_DDR_PWR_CON);  in pmu_sleep_restore()
749 	writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_SCU_PWR_CON);  in pmu_sleep_restore()
750 	writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_PLLPD_CON);  in pmu_sleep_restore()
751 	writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_CRU_PWR_CON0);  in pmu_sleep_restore()
752 	writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_CRU_PWR_CON1);  in pmu_sleep_restore()
1034 	pmu_base = dev_reg_base + RV1106_PMU_OFFSET;  in rv1106_suspend_init()
1093 	writel_relaxed(0x07ff07ff, pmu_base + RV1106_PMU_BIU_AUTO_CON);  in rv1106_suspend_init()