95 static void __iomem *ioc_base[5];  variable
202 	{ REG_REGION(0x000, 0x018, 4, &ioc_base[1], WMSK_VAL)},
203 	{ REG_REGION(0x080, 0x0b4, 4, &ioc_base[1], WMSK_VAL)},
204 	{ REG_REGION(0x180, 0x18c, 4, &ioc_base[1], WMSK_VAL)},
205 	{ REG_REGION(0x1c0, 0x1cc, 4, &ioc_base[1], WMSK_VAL)},
206 	{ REG_REGION(0x200, 0x20c, 4, &ioc_base[1], WMSK_VAL)},
207 	{ REG_REGION(0x240, 0x24c, 4, &ioc_base[1], WMSK_VAL)},
208 	{ REG_REGION(0x280, 0x28c, 4, &ioc_base[1], WMSK_VAL)},
209 	{ REG_REGION(0x2c0, 0x2cc, 4, &ioc_base[1], WMSK_VAL)},
210 	{ REG_REGION(0x2f4, 0x2f4, 4, &ioc_base[1], WMSK_VAL)},
213 	{ REG_REGION(0x020, 0x028, 4, &ioc_base[2], WMSK_VAL)},
214 	{ REG_REGION(0x0c0, 0x0d0, 4, &ioc_base[2], WMSK_VAL)},
215 	{ REG_REGION(0x190, 0x194, 4, &ioc_base[2], WMSK_VAL)},
216 	{ REG_REGION(0x1d0, 0x1d4, 4, &ioc_base[2], WMSK_VAL)},
217 	{ REG_REGION(0x210, 0x214, 4, &ioc_base[2], WMSK_VAL)},
218 	{ REG_REGION(0x250, 0x254, 4, &ioc_base[2], WMSK_VAL)},
219 	{ REG_REGION(0x290, 0x294, 4, &ioc_base[2], WMSK_VAL)},
220 	{ REG_REGION(0x2d0, 0x2d4, 4, &ioc_base[2], WMSK_VAL)},
223 	{ REG_REGION(0x040, 0x058, 4, &ioc_base[3], WMSK_VAL)},
224 	{ REG_REGION(0x100, 0x10c, 4, &ioc_base[3], WMSK_VAL)},
225 	{ REG_REGION(0x128, 0x134, 4, &ioc_base[3], WMSK_VAL)},
226 	{ REG_REGION(0x1a0, 0x1ac, 4, &ioc_base[3], WMSK_VAL)},
227 	{ REG_REGION(0x1e0, 0x1ec, 4, &ioc_base[3], WMSK_VAL)},
228 	{ REG_REGION(0x220, 0x22c, 4, &ioc_base[3], WMSK_VAL)},
229 	{ REG_REGION(0x260, 0x26c, 4, &ioc_base[3], WMSK_VAL)},
230 	{ REG_REGION(0x2a0, 0x2ac, 4, &ioc_base[3], WMSK_VAL)},
231 	{ REG_REGION(0x2e0, 0x2ec, 4, &ioc_base[3], WMSK_VAL)},
232 	{ REG_REGION(0x2f4, 0x2f4, 4, &ioc_base[3], WMSK_VAL)},
504 		writel_relaxed(BITS_WITH_WMASK(0x4, 0xf, 0), ioc_base[0] + 0);  in pvtm_32k_config()
616 	ddr_data.ioc1_1a_iomux_l = readl_relaxed(ioc_base[1] + 0);  in pmu_sleep_config()
694 	writel_relaxed(BITS_WITH_WMASK(0x1, 0xf, 12), ioc_base[0] + 0);  in pmu_sleep_config()
698 	writel_relaxed(BITS_WITH_WMASK(0x1, 0xf, 4), ioc_base[1] + 0);  in pmu_sleep_config()
755 		       ioc_base[1] + 0);  in pmu_sleep_restore()
766 	ddr_data.ioc0_1a_iomux_l = readl_relaxed(ioc_base[0] + 0);  in soc_sleep_config()
794 		       ioc_base[0] + 0);  in soc_sleep_restore()
810 		writel_relaxed(BITS_WITH_WMASK(func, 0xf, sft), ioc_base[0] + 0);  in gpio0_set_iomux()
812 		writel_relaxed(BITS_WITH_WMASK(func, 0xf, sft), ioc_base[0] + 4);  in gpio0_set_iomux()
819 	writel_relaxed(BITS_WITH_WMASK(pull, 0x3, sft), ioc_base[0] + 0x38);  in gpio0_set_pull()
836 	ddr_data.gpio0a_iomux_l = readl_relaxed(ioc_base[0] + 0);  in gpio_config()
837 	ddr_data.gpio0a_iomux_h = readl_relaxed(ioc_base[0] + 0x4);  in gpio_config()
838 	ddr_data.gpio0a0_pull = readl_relaxed(ioc_base[0] + 0x38);  in gpio_config()
879 	writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l), ioc_base[0] + 0);  in gpio_restore()
880 	writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h), ioc_base[0] + 0x4);  in gpio_restore()
882 	writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a0_pull), ioc_base[0] + 0x38);  in gpio_restore()
1066 	ioc_base[0] = dev_reg_base + RV1106_GPIO0IOC_OFFSET;  in rv1106_suspend_init()
1067 	ioc_base[1] = dev_reg_base + RV1106_GPIO1IOC_OFFSET;  in rv1106_suspend_init()
1068 	ioc_base[2] = dev_reg_base + RV1106_GPIO2IOC_OFFSET;  in rv1106_suspend_init()
1069 	ioc_base[3] = dev_reg_base + RV1106_GPIO3IOC_OFFSET;  in rv1106_suspend_init()
1070 	ioc_base[4] = dev_reg_base + RV1106_GPIO4IOC_OFFSET;  in rv1106_suspend_init()