96 static void __iomem *gpio_base[5];  variable
235 	{ REG_REGION(0x000, 0x00c, 4, &gpio_base[1], WMSK_VAL)},
236 	{ REG_REGION(0x018, 0x044, 4, &gpio_base[1], WMSK_VAL)},
237 	{ REG_REGION(0x048, 0x048, 4, &gpio_base[1], 0)},
238 	{ REG_REGION(0x060, 0x064, 4, &gpio_base[1], WMSK_VAL)},
239 	{ REG_REGION(0x100, 0x108, 4, &gpio_base[1], WMSK_VAL)},
240 	{ REG_REGION(0x010, 0x014, 4, &gpio_base[1], WMSK_VAL)},
242 	{ REG_REGION(0x000, 0x00c, 4, &gpio_base[2], WMSK_VAL)},
243 	{ REG_REGION(0x018, 0x044, 4, &gpio_base[2], WMSK_VAL)},
244 	{ REG_REGION(0x048, 0x048, 4, &gpio_base[2], 0)},
245 	{ REG_REGION(0x060, 0x064, 4, &gpio_base[2], WMSK_VAL)},
246 	{ REG_REGION(0x100, 0x108, 4, &gpio_base[2], WMSK_VAL)},
247 	{ REG_REGION(0x010, 0x014, 4, &gpio_base[2], WMSK_VAL)},
249 	{ REG_REGION(0x000, 0x00c, 4, &gpio_base[3], WMSK_VAL)},
250 	{ REG_REGION(0x018, 0x044, 4, &gpio_base[3], WMSK_VAL)},
251 	{ REG_REGION(0x048, 0x048, 4, &gpio_base[3], 0)},
252 	{ REG_REGION(0x060, 0x064, 4, &gpio_base[3], WMSK_VAL)},
253 	{ REG_REGION(0x100, 0x108, 4, &gpio_base[3], WMSK_VAL)},
254 	{ REG_REGION(0x010, 0x014, 4, &gpio_base[3], WMSK_VAL)},
337 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_EN_L));	\
339 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_EN_H));	\
341 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_MASK_L));	\
343 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_MASK_H));	\
345 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_STATUS));	\
347 		rkpm_printhex(readl_relaxed(gpio_base[id] + RV1106_GPIO_INT_RAWSTATUS));\
741 	ddr_data.gpio0_int_st = readl_relaxed(gpio_base[0] + RV1106_GPIO_INT_STATUS);  in pmu_sleep_restore()
828 			       gpio_base[0] + RV1106_GPIO_SWPORT_DDR_L);  in gpio0_set_direct()
831 			       gpio_base[0] + RV1106_GPIO_SWPORT_DDR_H);  in gpio0_set_direct()
839 	ddr_data.gpio0_ddr_l = readl_relaxed(gpio_base[0] + RV1106_GPIO_SWPORT_DDR_L);  in gpio_config()
840 	ddr_data.gpio0_ddr_h = readl_relaxed(gpio_base[0] + RV1106_GPIO_SWPORT_DDR_H);  in gpio_config()
885 		       gpio_base[0] + RV1106_GPIO_SWPORT_DDR_L);  in gpio_restore()
887 		       gpio_base[0] + RV1106_GPIO_SWPORT_DDR_H);  in gpio_restore()
1072 	gpio_base[0] = dev_reg_base + RV1106_GPIO0_OFFSET;  in rv1106_suspend_init()
1073 	gpio_base[1] = dev_reg_base + RV1106_GPIO1_OFFSET;  in rv1106_suspend_init()
1074 	gpio_base[2] = dev_reg_base + RV1106_GPIO2_OFFSET;  in rv1106_suspend_init()
1075 	gpio_base[3] = dev_reg_base + RV1106_GPIO3_OFFSET;  in rv1106_suspend_init()
1076 	gpio_base[4] = dev_reg_base + RV1106_GPIO4_OFFSET;  in rv1106_suspend_init()