Lines Matching refs:ddr_data

57 static struct rv1106_sleep_ddr_data ddr_data;  variable
353 u32 pmu_int_st = ddr_data.pmu_wkup_int_st; in rv1106_dbg_pmu_wkup_src()
364 rkpm_printhex(ddr_data.gpio0_int_st); in rv1106_dbg_pmu_wkup_src()
418 ddr_data.cru_gate_con[i] = in clock_suspend()
424 ddr_data.pmucru_gate_con[i] = in clock_suspend()
430 ddr_data.pericru_gate_con[i] = in clock_suspend()
436 ddr_data.npucru_gate_con[i] = in clock_suspend()
442 ddr_data.venccru_gate_con[i] = in clock_suspend()
448 ddr_data.vicru_gate_con[i] = in clock_suspend()
454 ddr_data.vocru_gate_con[i] = in clock_suspend()
465 writel_relaxed(WITH_16BITS_WMSK(ddr_data.cru_gate_con[i]), in clock_resume()
469 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmucru_gate_con[i]), in clock_resume()
473 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pericru_gate_con[i]), in clock_resume()
477 writel_relaxed(WITH_16BITS_WMSK(ddr_data.npucru_gate_con[i]), in clock_resume()
481 writel_relaxed(WITH_16BITS_WMSK(ddr_data.venccru_gate_con[i]), in clock_resume()
485 writel_relaxed(WITH_16BITS_WMSK(ddr_data.vicru_gate_con[i]), in clock_resume()
489 writel_relaxed(WITH_16BITS_WMSK(ddr_data.vocru_gate_con[i]), in clock_resume()
499 ddr_data.pmucru_sel_con7 = in pvtm_32k_config()
561 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmucru_sel_con7), in pvtm_32k_config_restore()
569 ddr_data.ddrc_pwrctrl = readl_relaxed(ddrc_base + 0x30); in ddr_sleep_config()
570 ddr_data.ddrgrf_con1 = readl_relaxed(ddrgrf_base + RV1106_DDRGRF_CON(1)); in ddr_sleep_config()
571 ddr_data.ddrgrf_con2 = readl_relaxed(ddrgrf_base + RV1106_DDRGRF_CON(2)); in ddr_sleep_config()
572 ddr_data.ddrgrf_con3 = readl_relaxed(ddrgrf_base + RV1106_DDRGRF_CON(3)); in ddr_sleep_config()
573 ddr_data.ddrc_dfilpcfg0 = readl_relaxed(ddrc_base + 0x198); in ddr_sleep_config()
574 ddr_data.pmugrf_soc_con0 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(0)); in ddr_sleep_config()
603 writel_relaxed(WITH_16BITS_WMSK(ddr_data.ddrgrf_con3), in ddr_sleep_config_restore()
613 ddr_data.pmugrf_soc_con1 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(1)); in pmu_sleep_config()
614 ddr_data.pmugrf_soc_con4 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(4)); in pmu_sleep_config()
615 ddr_data.pmugrf_soc_con5 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(5)); in pmu_sleep_config()
616 ddr_data.ioc1_1a_iomux_l = readl_relaxed(ioc_base[1] + 0); in pmu_sleep_config()
740 ddr_data.pmu_wkup_int_st = readl_relaxed(pmu_base + RV1106_PMU_WAKEUP_INT_ST); in pmu_sleep_restore()
741 ddr_data.gpio0_int_st = readl_relaxed(gpio_base[0] + RV1106_GPIO_INT_STATUS); in pmu_sleep_restore()
754 writel_relaxed(WITH_16BITS_WMSK(ddr_data.ioc1_1a_iomux_l), in pmu_sleep_restore()
756 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con1), in pmu_sleep_restore()
758 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con4), in pmu_sleep_restore()
760 writel_relaxed(WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con5), in pmu_sleep_restore()
766 ddr_data.ioc0_1a_iomux_l = readl_relaxed(ioc_base[0] + 0); in soc_sleep_config()
793 writel_relaxed(WITH_16BITS_WMSK(ddr_data.ioc0_1a_iomux_l), in soc_sleep_restore()
836 ddr_data.gpio0a_iomux_l = readl_relaxed(ioc_base[0] + 0); in gpio_config()
837 ddr_data.gpio0a_iomux_h = readl_relaxed(ioc_base[0] + 0x4); in gpio_config()
838 ddr_data.gpio0a0_pull = readl_relaxed(ioc_base[0] + 0x38); in gpio_config()
839 ddr_data.gpio0_ddr_l = readl_relaxed(gpio_base[0] + RV1106_GPIO_SWPORT_DDR_L); in gpio_config()
840 ddr_data.gpio0_ddr_h = readl_relaxed(gpio_base[0] + RV1106_GPIO_SWPORT_DDR_H); in gpio_config()
879 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l), ioc_base[0] + 0); in gpio_restore()
880 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h), ioc_base[0] + 0x4); in gpio_restore()
882 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a0_pull), ioc_base[0] + 0x38); in gpio_restore()
884 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0_ddr_l), in gpio_restore()
886 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0_ddr_h), in gpio_restore()