Lines Matching refs:WMSK_VAL
99 #define WMSK_VAL 0xffff0000 macro
103 { REG_REGION(0x300, 0x310, 4, &corecru_base, WMSK_VAL)},
104 { REG_REGION(0x800, 0x804, 4, &corecru_base, WMSK_VAL)},
109 { REG_REGION(0x020, 0x030, 4, &coresgrf_base, WMSK_VAL)},
110 { REG_REGION(0x040, 0x040, 4, &coresgrf_base, WMSK_VAL)},
114 { REG_REGION(0x004, 0x004, 4, &coregrf_base, WMSK_VAL)},
117 { REG_REGION(0x000, 0x000, 4, &coregrf_base, WMSK_VAL)},
118 { REG_REGION(0x02c, 0x02c, 4, &coregrf_base, WMSK_VAL)},
119 { REG_REGION(0x038, 0x03c, 4, &coregrf_base, WMSK_VAL)},
134 { REG_REGION(0x000, 0x004, 4, &cru_base, WMSK_VAL)},
136 { REG_REGION(0x00c, 0x010, 4, &cru_base, WMSK_VAL)},
137 { REG_REGION(0x020, 0x024, 4, &cru_base, WMSK_VAL)},
139 { REG_REGION(0x02c, 0x030, 4, &cru_base, WMSK_VAL)},
140 { REG_REGION(0x060, 0x064, 4, &cru_base, WMSK_VAL)},
142 { REG_REGION(0x06c, 0x070, 4, &cru_base, WMSK_VAL)},
145 { REG_REGION(0x300, 0x310, 4, &cru_base, WMSK_VAL)},
146 { REG_REGION(0x314, 0x34c, 8, &cru_base, WMSK_VAL)},
148 { REG_REGION(0x354, 0x360, 4, &cru_base, WMSK_VAL)},
149 { REG_REGION(0x364, 0x37c, 8, &cru_base, WMSK_VAL)},
151 { REG_REGION(0x384, 0x384, 4, &cru_base, WMSK_VAL)},
152 { REG_REGION(0x800, 0x80c, 4, &cru_base, WMSK_VAL)},
155 { REG_REGION(0xc14, 0xc28, 4, &cru_base, WMSK_VAL)},
158 { REG_REGION(0x300, 0x300, 4, &npucru_base, WMSK_VAL)},
159 { REG_REGION(0x800, 0x804, 4, &npucru_base, WMSK_VAL)},
166 { REG_REGION(0x304, 0x32c, 4, &pericru_base, WMSK_VAL)},
167 { REG_REGION(0x800, 0x81c, 4, &pericru_base, WMSK_VAL)},
172 { REG_REGION(0x020, 0x030, 4, &perisgrf_base, WMSK_VAL)},
173 { REG_REGION(0x080, 0x0a4, 4, &perisgrf_base, WMSK_VAL)},
174 { REG_REGION(0x0b8, 0x0bc, 4, &perisgrf_base, WMSK_VAL)},
177 { REG_REGION(0x300, 0x30c, 4, &vicru_base, WMSK_VAL)},
178 { REG_REGION(0x800, 0x808, 4, &vicru_base, WMSK_VAL)},
185 { REG_REGION(0x300, 0x30c, 4, &vocru_base, WMSK_VAL)},
186 { REG_REGION(0x800, 0x80c, 4, &vocru_base, WMSK_VAL)},
191 { REG_REGION(0x018, 0x018, 4, &vosgrf_base, WMSK_VAL)},
194 { REG_REGION(0x300, 0x304, 4, &venccru_base, WMSK_VAL)},
195 { REG_REGION(0x800, 0x808, 4, &venccru_base, WMSK_VAL)},
202 { REG_REGION(0x000, 0x018, 4, &ioc_base[1], WMSK_VAL)},
203 { REG_REGION(0x080, 0x0b4, 4, &ioc_base[1], WMSK_VAL)},
204 { REG_REGION(0x180, 0x18c, 4, &ioc_base[1], WMSK_VAL)},
205 { REG_REGION(0x1c0, 0x1cc, 4, &ioc_base[1], WMSK_VAL)},
206 { REG_REGION(0x200, 0x20c, 4, &ioc_base[1], WMSK_VAL)},
207 { REG_REGION(0x240, 0x24c, 4, &ioc_base[1], WMSK_VAL)},
208 { REG_REGION(0x280, 0x28c, 4, &ioc_base[1], WMSK_VAL)},
209 { REG_REGION(0x2c0, 0x2cc, 4, &ioc_base[1], WMSK_VAL)},
210 { REG_REGION(0x2f4, 0x2f4, 4, &ioc_base[1], WMSK_VAL)},
213 { REG_REGION(0x020, 0x028, 4, &ioc_base[2], WMSK_VAL)},
214 { REG_REGION(0x0c0, 0x0d0, 4, &ioc_base[2], WMSK_VAL)},
215 { REG_REGION(0x190, 0x194, 4, &ioc_base[2], WMSK_VAL)},
216 { REG_REGION(0x1d0, 0x1d4, 4, &ioc_base[2], WMSK_VAL)},
217 { REG_REGION(0x210, 0x214, 4, &ioc_base[2], WMSK_VAL)},
218 { REG_REGION(0x250, 0x254, 4, &ioc_base[2], WMSK_VAL)},
219 { REG_REGION(0x290, 0x294, 4, &ioc_base[2], WMSK_VAL)},
220 { REG_REGION(0x2d0, 0x2d4, 4, &ioc_base[2], WMSK_VAL)},
223 { REG_REGION(0x040, 0x058, 4, &ioc_base[3], WMSK_VAL)},
224 { REG_REGION(0x100, 0x10c, 4, &ioc_base[3], WMSK_VAL)},
225 { REG_REGION(0x128, 0x134, 4, &ioc_base[3], WMSK_VAL)},
226 { REG_REGION(0x1a0, 0x1ac, 4, &ioc_base[3], WMSK_VAL)},
227 { REG_REGION(0x1e0, 0x1ec, 4, &ioc_base[3], WMSK_VAL)},
228 { REG_REGION(0x220, 0x22c, 4, &ioc_base[3], WMSK_VAL)},
229 { REG_REGION(0x260, 0x26c, 4, &ioc_base[3], WMSK_VAL)},
230 { REG_REGION(0x2a0, 0x2ac, 4, &ioc_base[3], WMSK_VAL)},
231 { REG_REGION(0x2e0, 0x2ec, 4, &ioc_base[3], WMSK_VAL)},
232 { REG_REGION(0x2f4, 0x2f4, 4, &ioc_base[3], WMSK_VAL)},
235 { REG_REGION(0x000, 0x00c, 4, &gpio_base[1], WMSK_VAL)},
236 { REG_REGION(0x018, 0x044, 4, &gpio_base[1], WMSK_VAL)},
238 { REG_REGION(0x060, 0x064, 4, &gpio_base[1], WMSK_VAL)},
239 { REG_REGION(0x100, 0x108, 4, &gpio_base[1], WMSK_VAL)},
240 { REG_REGION(0x010, 0x014, 4, &gpio_base[1], WMSK_VAL)},
242 { REG_REGION(0x000, 0x00c, 4, &gpio_base[2], WMSK_VAL)},
243 { REG_REGION(0x018, 0x044, 4, &gpio_base[2], WMSK_VAL)},
245 { REG_REGION(0x060, 0x064, 4, &gpio_base[2], WMSK_VAL)},
246 { REG_REGION(0x100, 0x108, 4, &gpio_base[2], WMSK_VAL)},
247 { REG_REGION(0x010, 0x014, 4, &gpio_base[2], WMSK_VAL)},
249 { REG_REGION(0x000, 0x00c, 4, &gpio_base[3], WMSK_VAL)},
250 { REG_REGION(0x018, 0x044, 4, &gpio_base[3], WMSK_VAL)},
252 { REG_REGION(0x060, 0x064, 4, &gpio_base[3], WMSK_VAL)},
253 { REG_REGION(0x100, 0x108, 4, &gpio_base[3], WMSK_VAL)},
254 { REG_REGION(0x010, 0x014, 4, &gpio_base[3], WMSK_VAL)},