Lines Matching +full:0 +full:x198
99 #define WMSK_VAL 0xffff0000
103 { REG_REGION(0x300, 0x310, 4, &corecru_base, WMSK_VAL)},
104 { REG_REGION(0x800, 0x804, 4, &corecru_base, WMSK_VAL)},
107 { REG_REGION(0x004, 0x014, 4, &coresgrf_base, 0)},
108 { REG_REGION(0x000, 0x000, 4, &coresgrf_base, 0)},
109 { REG_REGION(0x020, 0x030, 4, &coresgrf_base, WMSK_VAL)},
110 { REG_REGION(0x040, 0x040, 4, &coresgrf_base, WMSK_VAL)},
111 { REG_REGION(0x044, 0x044, 4, &coresgrf_base, 0)},
114 { REG_REGION(0x004, 0x004, 4, &coregrf_base, WMSK_VAL)},
115 { REG_REGION(0x008, 0x010, 4, &coregrf_base, 0)},
116 { REG_REGION(0x024, 0x028, 4, &coregrf_base, 0)},
117 { REG_REGION(0x000, 0x000, 4, &coregrf_base, WMSK_VAL)},
118 { REG_REGION(0x02c, 0x02c, 4, &coregrf_base, WMSK_VAL)},
119 { REG_REGION(0x038, 0x03c, 4, &coregrf_base, WMSK_VAL)},
124 { REG_REGION(0x000, 0x03c, 4, &firewall_ddr_base, 0)},
125 { REG_REGION(0x040, 0x06c, 4, &firewall_ddr_base, 0)},
126 { REG_REGION(0x0f0, 0x0f0, 4, &firewall_ddr_base, 0)},
129 { REG_REGION(0x000, 0x01c, 4, &firewall_syssram_base, 0)},
130 { REG_REGION(0x040, 0x054, 4, &firewall_syssram_base, 0)},
131 { REG_REGION(0x0f0, 0x0f0, 4, &firewall_syssram_base, 0)},
134 { REG_REGION(0x000, 0x004, 4, &cru_base, WMSK_VAL)},
135 { REG_REGION(0x008, 0x008, 4, &cru_base, 0)},
136 { REG_REGION(0x00c, 0x010, 4, &cru_base, WMSK_VAL)},
137 { REG_REGION(0x020, 0x024, 4, &cru_base, WMSK_VAL)},
138 { REG_REGION(0x028, 0x028, 4, &cru_base, 0)},
139 { REG_REGION(0x02c, 0x030, 4, &cru_base, WMSK_VAL)},
140 { REG_REGION(0x060, 0x064, 4, &cru_base, WMSK_VAL)},
141 { REG_REGION(0x068, 0x068, 4, &cru_base, 0)},
142 { REG_REGION(0x06c, 0x070, 4, &cru_base, WMSK_VAL)},
143 { REG_REGION(0x140, 0x1bc, 4, &cru_base, 0)},
144 /* { REG_REGION(0x280, 0x280, 4, &cru_base, WMSK_VAL)}, */
145 { REG_REGION(0x300, 0x310, 4, &cru_base, WMSK_VAL)},
146 { REG_REGION(0x314, 0x34c, 8, &cru_base, WMSK_VAL)},
147 { REG_REGION(0x318, 0x350, 8, &cru_base, 0)},
148 { REG_REGION(0x354, 0x360, 4, &cru_base, WMSK_VAL)},
149 { REG_REGION(0x364, 0x37c, 8, &cru_base, WMSK_VAL)},
150 { REG_REGION(0x368, 0x380, 8, &cru_base, 0)},
151 { REG_REGION(0x384, 0x384, 4, &cru_base, WMSK_VAL)},
152 { REG_REGION(0x800, 0x80c, 4, &cru_base, WMSK_VAL)},
153 { REG_REGION(0xc00, 0xc00, 4, &cru_base, 0)},
154 { REG_REGION(0xc10, 0xc10, 4, &cru_base, 0)},
155 { REG_REGION(0xc14, 0xc28, 4, &cru_base, WMSK_VAL)},
158 { REG_REGION(0x300, 0x300, 4, &npucru_base, WMSK_VAL)},
159 { REG_REGION(0x800, 0x804, 4, &npucru_base, WMSK_VAL)},
162 { REG_REGION(0x004, 0x014, 4, &npusgrf_base, 0)},
163 { REG_REGION(0x000, 0x000, 4, &npusgrf_base, 0)},
166 { REG_REGION(0x304, 0x32c, 4, &pericru_base, WMSK_VAL)},
167 { REG_REGION(0x800, 0x81c, 4, &pericru_base, WMSK_VAL)},
170 { REG_REGION(0x004, 0x014, 4, &perisgrf_base, 0)},
171 { REG_REGION(0x000, 0x000, 4, &perisgrf_base, 0)},
172 { REG_REGION(0x020, 0x030, 4, &perisgrf_base, WMSK_VAL)},
173 { REG_REGION(0x080, 0x0a4, 4, &perisgrf_base, WMSK_VAL)},
174 { REG_REGION(0x0b8, 0x0bc, 4, &perisgrf_base, WMSK_VAL)},
177 { REG_REGION(0x300, 0x30c, 4, &vicru_base, WMSK_VAL)},
178 { REG_REGION(0x800, 0x808, 4, &vicru_base, WMSK_VAL)},
181 { REG_REGION(0x004, 0x014, 4, &visgrf_base, 0)},
182 { REG_REGION(0x000, 0x000, 4, &visgrf_base, 0)},
185 { REG_REGION(0x300, 0x30c, 4, &vocru_base, WMSK_VAL)},
186 { REG_REGION(0x800, 0x80c, 4, &vocru_base, WMSK_VAL)},
189 { REG_REGION(0x004, 0x014, 4, &vosgrf_base, 0)},
190 { REG_REGION(0x000, 0x000, 4, &vosgrf_base, 0)},
191 { REG_REGION(0x018, 0x018, 4, &vosgrf_base, WMSK_VAL)},
194 { REG_REGION(0x300, 0x304, 4, &venccru_base, WMSK_VAL)},
195 { REG_REGION(0x800, 0x808, 4, &venccru_base, WMSK_VAL)},
198 { REG_REGION(0x004, 0x014, 4, &vencsgrf_base, 0)},
199 { REG_REGION(0x000, 0x000, 4, &vencsgrf_base, 0)},
202 { REG_REGION(0x000, 0x018, 4, &ioc_base[1], WMSK_VAL)},
203 { REG_REGION(0x080, 0x0b4, 4, &ioc_base[1], WMSK_VAL)},
204 { REG_REGION(0x180, 0x18c, 4, &ioc_base[1], WMSK_VAL)},
205 { REG_REGION(0x1c0, 0x1cc, 4, &ioc_base[1], WMSK_VAL)},
206 { REG_REGION(0x200, 0x20c, 4, &ioc_base[1], WMSK_VAL)},
207 { REG_REGION(0x240, 0x24c, 4, &ioc_base[1], WMSK_VAL)},
208 { REG_REGION(0x280, 0x28c, 4, &ioc_base[1], WMSK_VAL)},
209 { REG_REGION(0x2c0, 0x2cc, 4, &ioc_base[1], WMSK_VAL)},
210 { REG_REGION(0x2f4, 0x2f4, 4, &ioc_base[1], WMSK_VAL)},
213 { REG_REGION(0x020, 0x028, 4, &ioc_base[2], WMSK_VAL)},
214 { REG_REGION(0x0c0, 0x0d0, 4, &ioc_base[2], WMSK_VAL)},
215 { REG_REGION(0x190, 0x194, 4, &ioc_base[2], WMSK_VAL)},
216 { REG_REGION(0x1d0, 0x1d4, 4, &ioc_base[2], WMSK_VAL)},
217 { REG_REGION(0x210, 0x214, 4, &ioc_base[2], WMSK_VAL)},
218 { REG_REGION(0x250, 0x254, 4, &ioc_base[2], WMSK_VAL)},
219 { REG_REGION(0x290, 0x294, 4, &ioc_base[2], WMSK_VAL)},
220 { REG_REGION(0x2d0, 0x2d4, 4, &ioc_base[2], WMSK_VAL)},
223 { REG_REGION(0x040, 0x058, 4, &ioc_base[3], WMSK_VAL)},
224 { REG_REGION(0x100, 0x10c, 4, &ioc_base[3], WMSK_VAL)},
225 { REG_REGION(0x128, 0x134, 4, &ioc_base[3], WMSK_VAL)},
226 { REG_REGION(0x1a0, 0x1ac, 4, &ioc_base[3], WMSK_VAL)},
227 { REG_REGION(0x1e0, 0x1ec, 4, &ioc_base[3], WMSK_VAL)},
228 { REG_REGION(0x220, 0x22c, 4, &ioc_base[3], WMSK_VAL)},
229 { REG_REGION(0x260, 0x26c, 4, &ioc_base[3], WMSK_VAL)},
230 { REG_REGION(0x2a0, 0x2ac, 4, &ioc_base[3], WMSK_VAL)},
231 { REG_REGION(0x2e0, 0x2ec, 4, &ioc_base[3], WMSK_VAL)},
232 { REG_REGION(0x2f4, 0x2f4, 4, &ioc_base[3], WMSK_VAL)},
235 { REG_REGION(0x000, 0x00c, 4, &gpio_base[1], WMSK_VAL)},
236 { REG_REGION(0x018, 0x044, 4, &gpio_base[1], WMSK_VAL)},
237 { REG_REGION(0x048, 0x048, 4, &gpio_base[1], 0)},
238 { REG_REGION(0x060, 0x064, 4, &gpio_base[1], WMSK_VAL)},
239 { REG_REGION(0x100, 0x108, 4, &gpio_base[1], WMSK_VAL)},
240 { REG_REGION(0x010, 0x014, 4, &gpio_base[1], WMSK_VAL)},
242 { REG_REGION(0x000, 0x00c, 4, &gpio_base[2], WMSK_VAL)},
243 { REG_REGION(0x018, 0x044, 4, &gpio_base[2], WMSK_VAL)},
244 { REG_REGION(0x048, 0x048, 4, &gpio_base[2], 0)},
245 { REG_REGION(0x060, 0x064, 4, &gpio_base[2], WMSK_VAL)},
246 { REG_REGION(0x100, 0x108, 4, &gpio_base[2], WMSK_VAL)},
247 { REG_REGION(0x010, 0x014, 4, &gpio_base[2], WMSK_VAL)},
249 { REG_REGION(0x000, 0x00c, 4, &gpio_base[3], WMSK_VAL)},
250 { REG_REGION(0x018, 0x044, 4, &gpio_base[3], WMSK_VAL)},
251 { REG_REGION(0x048, 0x048, 4, &gpio_base[3], 0)},
252 { REG_REGION(0x060, 0x064, 4, &gpio_base[3], WMSK_VAL)},
253 { REG_REGION(0x100, 0x108, 4, &gpio_base[3], WMSK_VAL)},
254 { REG_REGION(0x010, 0x014, 4, &gpio_base[3], WMSK_VAL)},
257 { REG_REGION(0x00, 0x04, 4, &nstimer_base, 0)},
258 { REG_REGION(0x10, 0x10, 4, &nstimer_base, 0)},
259 { REG_REGION(0x20, 0x24, 4, &nstimer_base, 0)},
260 { REG_REGION(0x30, 0x30, 4, &nstimer_base, 0)},
261 { REG_REGION(0x40, 0x44, 4, &nstimer_base, 0)},
262 { REG_REGION(0x50, 0x50, 4, &nstimer_base, 0)},
263 { REG_REGION(0x60, 0x64, 4, &nstimer_base, 0)},
264 { REG_REGION(0x70, 0x70, 4, &nstimer_base, 0)},
265 { REG_REGION(0x80, 0x84, 4, &nstimer_base, 0)},
266 { REG_REGION(0x90, 0x90, 4, &nstimer_base, 0)},
267 { REG_REGION(0xa0, 0xa4, 4, &nstimer_base, 0)},
268 { REG_REGION(0xb0, 0xb0, 4, &nstimer_base, 0)},
271 { REG_REGION(0x00, 0x04, 4, &stimer_base, 0)},
272 { REG_REGION(0x10, 0x10, 4, &stimer_base, 0)},
273 { REG_REGION(0x20, 0x24, 4, &stimer_base, 0)},
274 { REG_REGION(0x30, 0x30, 4, &stimer_base, 0)},
286 while (delay-- >= 0) { in pm_pll_wait_lock()
294 if (delay <= 0) { in pm_pll_wait_lock()
318 writel_relaxed(byte, uartdbg_base + 0x0); in uart_wrtie_byte()
320 while (!(readl_relaxed(uartdbg_base + 0x14) & 0x40)) in uart_wrtie_byte()
349 } while (0)
388 RV1106_DUMP_GPIO_INTEN(0); in rv1106_dbg_irq_prepare()
400 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr)); in rv1106_l2_config()
417 for (i = 0; i < RV1106_CRU_GATE_CON_NUM; i++) { in clock_suspend()
420 writel_relaxed(0xffff0000, cru_base + RV1106_CRU_GATE_CON(i)); in clock_suspend()
423 for (i = 0; i < RV1106_PMUCRU_GATE_CON_NUM; i++) { in clock_suspend()
426 writel_relaxed(0xffff0000, pmucru_base + RV1106_PMUCRU_GATE_CON(i)); in clock_suspend()
429 for (i = 0; i < RV1106_PERICRU_GATE_CON_NUM; i++) { in clock_suspend()
432 writel_relaxed(0xffff0000, pericru_base + RV1106_PERICRU_GATE_CON(i)); in clock_suspend()
435 for (i = 0; i < RV1106_NPUCRU_GATE_CON_NUM; i++) { in clock_suspend()
438 writel_relaxed(0xffff0000, npucru_base + RV1106_NPUCRU_GATE_CON(i)); in clock_suspend()
441 for (i = 0; i < RV1106_VENCCRU_GATE_CON_NUM; i++) { in clock_suspend()
444 writel_relaxed(0xffff0000, venccru_base + RV1106_VENCCRU_GATE_CON(i)); in clock_suspend()
447 for (i = 0; i < RV1106_VICRU_GATE_CON_NUM; i++) { in clock_suspend()
450 writel_relaxed(0xffff0000, vicru_base + RV1106_VICRU_GATE_CON(i)); in clock_suspend()
453 for (i = 0; i < RV1106_VOCRU_GATE_CON_NUM; i++) { in clock_suspend()
456 writel_relaxed(0xffff0000, vocru_base + RV1106_VOCRU_GATE_CON(i)); in clock_suspend()
464 for (i = 0; i < RV1106_CRU_GATE_CON_NUM; i++) in clock_resume()
468 for (i = 0; i < RV1106_PMUCRU_GATE_CON_NUM; i++) in clock_resume()
472 for (i = 0; i < RV1106_PERICRU_GATE_CON_NUM; i++) in clock_resume()
476 for (i = 0; i < RV1106_NPUCRU_GATE_CON_NUM; i++) in clock_resume()
480 for (i = 0; i < RV1106_VENCCRU_GATE_CON_NUM; i++) in clock_resume()
484 for (i = 0; i < RV1106_VICRU_GATE_CON_NUM; i++) in clock_resume()
488 for (i = 0; i < RV1106_VOCRU_GATE_CON_NUM; i++) in clock_resume()
503 writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 6), vigrf_base + 0x0); in pvtm_32k_config()
504 writel_relaxed(BITS_WITH_WMASK(0x4, 0xf, 0), ioc_base[0] + 0); in pvtm_32k_config()
505 writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 15), in pvtm_32k_config()
507 writel_relaxed(BITS_WITH_WMASK(0x1, 0x3, 0), in pvtm_32k_config()
510 writel_relaxed(BITS_WITH_WMASK(0, 0x3, 0), in pvtm_32k_config()
514 writel_relaxed(BITS_WITH_WMASK(0, 0x3, PVTM_START), in pvtm_32k_config()
515 pmupvtm_base + RV1106_PVTM_CON(0)); in pvtm_32k_config()
518 writel_relaxed(BITS_WITH_WMASK(0, 0x7, PVTM_OSC_SEL), in pvtm_32k_config()
519 pmupvtm_base + RV1106_PVTM_CON(0)); in pvtm_32k_config()
520 writel_relaxed(BITS_WITH_WMASK(1, 0x1, PVTM_OSC_EN), in pvtm_32k_config()
521 pmupvtm_base + RV1106_PVTM_CON(0)); in pvtm_32k_config()
522 writel_relaxed(BITS_WITH_WMASK(1, 0x1, PVTM_RND_SEED_EN), in pvtm_32k_config()
523 pmupvtm_base + RV1106_PVTM_CON(0)); in pvtm_32k_config()
526 writel_relaxed(BITS_WITH_WMASK(1, 0x1, PVTM_START), in pvtm_32k_config()
527 pmupvtm_base + RV1106_PVTM_CON(0)); in pvtm_32k_config()
535 while (!readl_relaxed(pmupvtm_base + RV1106_PVTM_STATUS(0)) & 0x1) in pvtm_32k_config()
541 if (pvtm_div > 0xfff) in pvtm_32k_config()
542 pvtm_div = 0xfff; in pvtm_32k_config()
548 writel_relaxed(BITS_WITH_WMASK(0x2, 0x3, 0), in pvtm_32k_config()
569 ddr_data.ddrc_pwrctrl = readl_relaxed(ddrc_base + 0x30); in ddr_sleep_config()
573 ddr_data.ddrc_dfilpcfg0 = readl_relaxed(ddrc_base + 0x198); in ddr_sleep_config()
574 ddr_data.pmugrf_soc_con0 = readl_relaxed(pmugrf_base + RV1106_PMUGRF_SOC_CON(0)); in ddr_sleep_config()
576 val = readl_relaxed(ddrc_base + 0x30); in ddr_sleep_config()
577 writel_relaxed(val & ~(BIT(0) | BIT(1)), ddrc_base + 0x30); in ddr_sleep_config()
580 writel_relaxed(BITS_WITH_WMASK(0x12, 0x1f, 0), ddrgrf_base + RV1106_DDRGRF_CON(1)); in ddr_sleep_config()
582 writel_relaxed(BITS_WITH_WMASK(0x3ff, 0x3ff, 0), ddrgrf_base + RV1106_DDRGRF_CON(2)); in ddr_sleep_config()
585 writel_relaxed(BITS_WITH_WMASK(0x3, 0x3, 8), ddrgrf_base + RV1106_DDRGRF_CON(3)); in ddr_sleep_config()
587 while ((readl_relaxed(ddrc_base + 0x4) & 0x7) != 0x1) in ddr_sleep_config()
590 val = readl_relaxed(ddrc_base + 0x198) & ~(0xf << 12 | 0xf << 4); in ddr_sleep_config()
591 val |= (0xa << 12 | 0xa << 4); in ddr_sleep_config()
592 writel_relaxed(val, ddrc_base + 0x198); in ddr_sleep_config()
594 val = readl_relaxed(ddrc_base + 0x198) | BIT(8) | BIT(0); in ddr_sleep_config()
595 writel_relaxed(val, ddrc_base + 0x198); in ddr_sleep_config()
598 writel_relaxed(BITS_WITH_WMASK(0x0, 0x7, 9), pmugrf_base + RV1106_PMUGRF_SOC_CON(0)); in ddr_sleep_config()
616 ddr_data.ioc1_1a_iomux_l = readl_relaxed(ioc_base[1] + 0); in pmu_sleep_config()
622 0; in pmu_sleep_config()
629 0; in pmu_sleep_config()
634 0; in pmu_sleep_config()
648 0; in pmu_sleep_config()
650 pmu_cru_con[0] = in pmu_sleep_config()
657 0; in pmu_sleep_config()
668 0; in pmu_sleep_config()
679 0; in pmu_sleep_config()
686 0; in pmu_sleep_config()
690 writel_relaxed(BITS_WITH_WMASK(0x4, 0x7, 0), pmugrf_base + RV1106_PMUGRF_SOC_CON(1)); in pmu_sleep_config()
692 writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 0), pmugrf_base + RV1106_PMUGRF_SOC_CON(1)); in pmu_sleep_config()
694 writel_relaxed(BITS_WITH_WMASK(0x1, 0xf, 12), ioc_base[0] + 0); in pmu_sleep_config()
697 writel_relaxed(0xffffff01, pmu_base + RV1106_PMU_INFO_TX_CON); in pmu_sleep_config()
698 writel_relaxed(BITS_WITH_WMASK(0x1, 0xf, 4), ioc_base[1] + 0); in pmu_sleep_config()
714 writel_relaxed(0xffffffff, pmugrf_base + RV1106_PMUGRF_SOC_CON(4)); in pmu_sleep_config()
715 writel_relaxed(0xffffff47, pmugrf_base + RV1106_PMUGRF_SOC_CON(5)); in pmu_sleep_config()
717 writel_relaxed(0x00010001, pmu_base + RV1106_PMU_INT_MASK_CON); in pmu_sleep_config()
720 writel_relaxed(WITH_16BITS_WMSK(pmu_cru_con[0]), pmu_base + RV1106_PMU_CRU_PWR_CON0); in pmu_sleep_config()
730 writel_relaxed(0, pmugrf_base + RV1106_PMUGRF_OS_REG(9)); in pmu_sleep_config()
732 writel_relaxed(0, pmugrf_base + RV1106_PMUGRF_OS_REG(10)); in pmu_sleep_config()
741 ddr_data.gpio0_int_st = readl_relaxed(gpio_base[0] + RV1106_GPIO_INT_STATUS); in pmu_sleep_restore()
743 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_INFO_TX_CON); in pmu_sleep_restore()
744 writel_relaxed(0x00010000, pmu_base + RV1106_PMU_INT_MASK_CON); in pmu_sleep_restore()
745 writel_relaxed(0x00000000, pmu_base + RV1106_PMU_WAKEUP_INT_CON); in pmu_sleep_restore()
746 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_PWR_CON); in pmu_sleep_restore()
747 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_BIU_IDLE_CON); in pmu_sleep_restore()
748 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_DDR_PWR_CON); in pmu_sleep_restore()
749 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_SCU_PWR_CON); in pmu_sleep_restore()
750 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_PLLPD_CON); in pmu_sleep_restore()
751 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_CRU_PWR_CON0); in pmu_sleep_restore()
752 writel_relaxed(0xffff0000, pmu_base + RV1106_PMU_CRU_PWR_CON1); in pmu_sleep_restore()
755 ioc_base[1] + 0); in pmu_sleep_restore()
766 ddr_data.ioc0_1a_iomux_l = readl_relaxed(ioc_base[0] + 0); in soc_sleep_config()
770 pvtm_32k_config(0); in soc_sleep_config()
794 ioc_base[0] + 0); in soc_sleep_restore()
810 writel_relaxed(BITS_WITH_WMASK(func, 0xf, sft), ioc_base[0] + 0); in gpio0_set_iomux()
812 writel_relaxed(BITS_WITH_WMASK(func, 0xf, sft), ioc_base[0] + 4); in gpio0_set_iomux()
819 writel_relaxed(BITS_WITH_WMASK(pull, 0x3, sft), ioc_base[0] + 0x38); in gpio0_set_pull()
827 writel_relaxed(BITS_WITH_WMASK(out, 0x1, sft), in gpio0_set_direct()
828 gpio_base[0] + RV1106_GPIO_SWPORT_DDR_L); in gpio0_set_direct()
830 writel_relaxed(BITS_WITH_WMASK(out, 0x1, sft), in gpio0_set_direct()
831 gpio_base[0] + RV1106_GPIO_SWPORT_DDR_H); in gpio0_set_direct()
836 ddr_data.gpio0a_iomux_l = readl_relaxed(ioc_base[0] + 0); in gpio_config()
837 ddr_data.gpio0a_iomux_h = readl_relaxed(ioc_base[0] + 0x4); in gpio_config()
838 ddr_data.gpio0a0_pull = readl_relaxed(ioc_base[0] + 0x38); in gpio_config()
839 ddr_data.gpio0_ddr_l = readl_relaxed(gpio_base[0] + RV1106_GPIO_SWPORT_DDR_L); in gpio_config()
840 ddr_data.gpio0_ddr_h = readl_relaxed(gpio_base[0] + RV1106_GPIO_SWPORT_DDR_H); in gpio_config()
843 gpio0_set_iomux(0, 0); in gpio_config()
844 gpio0_set_pull(0, RV1106_GPIO_PULL_DOWN); in gpio_config()
845 gpio0_set_direct(0, 0); in gpio_config()
849 gpio0_set_iomux(1, 0); in gpio_config()
851 gpio0_set_direct(1, 0); in gpio_config()
854 gpio0_set_iomux(2, 0); in gpio_config()
856 gpio0_set_direct(2, 0); in gpio_config()
862 gpio0_set_iomux(4, 0); in gpio_config()
864 gpio0_set_direct(4, 0); in gpio_config()
867 gpio0_set_iomux(5, 0); in gpio_config()
869 gpio0_set_direct(5, 0); in gpio_config()
872 gpio0_set_iomux(6, 0); in gpio_config()
874 gpio0_set_direct(6, 0); in gpio_config()
879 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l), ioc_base[0] + 0); in gpio_restore()
880 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h), ioc_base[0] + 0x4); in gpio_restore()
882 writel_relaxed(WITH_16BITS_WMSK(ddr_data.gpio0a0_pull), ioc_base[0] + 0x38); in gpio_restore()
885 gpio_base[0] + RV1106_GPIO_SWPORT_DDR_L); in gpio_restore()
887 gpio_base[0] + RV1106_GPIO_SWPORT_DDR_H); in gpio_restore()
895 cru_mode = readl_relaxed(cru_base + 0x280); in vd_log_regs_save()
916 writel_relaxed(0x003f0000, cru_base + 0x280); in vd_log_regs_restore()
927 writel_relaxed(WITH_16BITS_WMSK(cru_mode), cru_base + 0x280); in vd_log_regs_restore()
968 rkpm_printch('0'); in rv1106_suspend_enter()
984 cpu_suspend(0, rockchip_lpmode_enter); in rv1106_suspend_enter()
999 rkpm_printch('0'); in rv1106_suspend_enter()
1011 return 0; in rv1106_suspend_enter()
1020 pr_info("%s map dev_reg 0x%x -> 0x%x\n", in rv1106_suspend_init()
1023 pr_err("%s: can't map dev_reg(0x%x)\n", __func__, RV1106_DEV_REG_BASE); in rv1106_suspend_init()
1025 gicd_base = dev_reg_base + RV1106_GIC_OFFSET + 0x1000; in rv1106_suspend_init()
1026 gicc_base = dev_reg_base + RV1106_GIC_OFFSET + 0x2000; in rv1106_suspend_init()
1066 ioc_base[0] = dev_reg_base + RV1106_GPIO0IOC_OFFSET; in rv1106_suspend_init()
1072 gpio_base[0] = dev_reg_base + RV1106_GPIO0_OFFSET; in rv1106_suspend_init()
1084 rv1106_bootram_sz + 0x50); in rv1106_suspend_init()
1088 writel_relaxed(BITS_WITH_WMASK(1, 0x1, 10), pmusgrf_base + RV1106_PMUSGRF_SOC_CON(1)); in rv1106_suspend_init()
1090 writel_relaxed(BITS_WITH_WMASK(0, 0x1, 10), pmusgrf_base + RV1106_PMUSGRF_SOC_CON(1)); in rv1106_suspend_init()
1093 writel_relaxed(0x07ff07ff, pmu_base + RV1106_PMU_BIU_AUTO_CON); in rv1106_suspend_init()
1098 return 0; in rv1106_suspend_init()