arm/mach-pxa/regs-u2d.h

1 /* SPDX-License-Identifier: GPL-2.0 */
21 #define U2DCR_DWRE	(1   << 16)	/* Device Remote Wake-up Feature */
32 #define U2DINT_CC		(1 << 31)	/* Interrupt - Configuration Change */
33 #define U2DINT_SOF		(1 << 30)	/* Interrupt - SOF */
34 #define U2DINT_USOF		(1 << 29)	/* Interrupt - micro SOF */
35 #define U2DINT_RU		(1 << 28)	/* Interrupt - Resume */
36 #define U2DINT_SU		(1 << 27)	/* Interrupt - Suspend */
37 #define U2DINT_RS		(1 << 26)	/* Interrupt - Reset */
38 #define U2DINT_DPE		(1 << 25)	/* Interrupt - Data Packet Error */
39 #define U2DINT_FIFOERR		(0x4)		/* Interrupt - endpoint FIFO error */
40 #define U2DINT_PACKETCMP	(0x2)		/* Interrupt - endpoint packet complete */
41 #define U2DINT_SPACKETCMP	(0x1)		/* Interrupt - endpoint short packet complete */
49 #define U2DOTGCR		(0x0020)	/* U2D OTG Control Register */
50 #define U2DOTGCR_OTGEN		(1 << 31)	/* On-The-Go Enable */
51 #define U2DOTGCR_AALTHNP	(1 << 30)	/* A-device Alternate Host Negotiation Protocal Port Support */
52 #define U2DOTGCR_AHNP		(1 << 29)	/* A-device Host Negotiation Protocal Support */
53 #define U2DOTGCR_BHNP		(1 << 28)	/* B-device Host Negotiation Protocal Enable */
57 #define U2DOTGCR_IESI		(1 << 13)	/* OTG interrupt Enable */
58 #define U2DOTGCR_ISSI		(1 << 12)	/* OTG interrupt status */
68 #define U2DOTGICR	(0x0024)	/* U2D OTG Interrupt Control Register */
69 #define U2DOTGISR	(0x0028)	/* U2D OTG Interrupt Status Register */
71 #define U2DOTGINT_SF	(1 << 17)	/* OTG Set Feature Command Received */
72 #define U2DOTGINT_SI	(1 << 16)	/* OTG Interrupt */
75 #define U2DOTGINT_RID	(1 << 12)	/* RXCMD OTG ID Change Interrupt Rise */
76 #define U2DOTGINT_RSE	(1 << 11)	/* RXCMD OTG Session End Interrupt Rise */
77 #define U2DOTGINT_RSV	(1 << 10)	/* RXCMD OTG Session Valid Interrupt Rise */
78 #define U2DOTGINT_RVV	(1 << 9)	/* RXCMD OTG Vbus Valid Interrupt Rise */
82 #define U2DOTGINT_FID	(1 << 4)	/* RXCMD OTG ID Change Interrupt Fall */
83 #define U2DOTGINT_FSE	(1 << 3)	/* RXCMD OTG Session End Interrupt Fall */
84 #define U2DOTGINT_FSV	(1 << 2)	/* RXCMD OTG Session Valid Interrupt Fall */
85 #define U2DOTGINT_FVV	(1 << 1)	/* RXCMD OTG Vbus Valid Interrupt Fall */
88 #define U2DOTGUSR	(0x002C)	/* U2D OTG ULPI Status Register */
90 #define U2DOTGUSR_S6A	(1 << 30)	/* ULPI Serial Mode (6-pin) Active */
91 #define U2DOTGUSR_S3A	(1 << 29)	/* ULPI Serial Mode (3-pin) Active */
95 #define U2DOTGUSR_ID	(1 << 4)	/* OTG IDGnd Status */
96 #define U2DOTGUSR_SE	(1 << 3)	/* OTG Session End Status */
97 #define U2DOTGUSR_SV	(1 << 2)	/* OTG Session Valid Status */
98 #define U2DOTGUSR_VV	(1 << 1)	/* OTG Vbus Valid Status */
101 #define U2DOTGUCR	(0x0030)	/* U2D OTG ULPI Control Register */
108 #define U2DP3CR		(0x0034)	/* U2D Port 3 Control Register */
109 #define U2DP3CR_P2SS	(0x3 << 8)	/* Host Port 2 Serial Mode Select */
110 #define U2DP3CR_P3SS	(0x7 << 4)	/* Host Port 3 Serial Mode Select */
111 #define U2DP3CR_VPVMBEN	(0x1 << 2)	/* Host Port 3 Vp/Vm Block Enable */
112 #define U2DP3CR_CFG	(0x3 << 0)	/* Host Port 3 Configuration */
114 #define U2DCSR0		(0x0100)	/* U2D Control/Status Register - Endpoint 0 */
125 #define U2DCSR(x)	(0x0100 + ((x) << 2))	/* U2D Control/Status Register - Endpoint x */
140 #define U2DBCR0		(0x0200)		/* U2D Byte Count Register - Endpoint 0 */
141 #define U2DBCR(x)	(0x0200 + ((x) << 2))	/* U2D Byte Count Register - Endpoint x */
143 #define U2DDR0		(0x0300)		/* U2D Data Register - Endpoint 0 */
145 #define U2DEPCR(x)	(0x0400 + ((x) << 2))	/* U2D Configuration Register - Endpoint x */
152 #define U2DEN0		(0x0504)		/* U2D Endpoint Information Register - Endpoint 0 */
153 #define U2DEN(x)	(0x0504 + ((x) << 2))	/* U2D Endpoint Information Register - Endpoint x */
156 #define U2DMACSR0		(0x1000)	/* U2DMA Control/Status Register - Channel 0 */
157 #define U2DMACSR(x)		(0x1000 + ((x) << 2))	/* U2DMA Control/Status Register - Channel x */
179 #define U2DMABR0	(0x1100)		/* U2DMA Branch Register - Channel 0 */
180 #define U2DMABR(x)      (0x1100 + (x) << 2)	/* U2DMA Branch Register - Channel x */
182 #define U2DMADADR0      (0x1200)		/* U2DMA Descriptor Address Register - Channel 0 */
183 #define U2DMADADR(x)    (0x1200 + (x) * 0x10)	/* U2DMA Descriptor Address Register - Channel x */
187 #define U2DMASADR0	(0x1204)		/* U2DMA Source Address Register - Channel 0 */
188 #define U2DMASADR(x)	(0x1204 + (x) * 0x10)	/* U2DMA Source Address Register - Channel x */
189 #define U2DMATADR0	(0x1208)		/* U2DMA Target Address Register - Channel 0 */
190 #define U2DMATADR(x)	(0x1208 + (x) * 0x10)	/* U2DMA Target Address Register - Channel x */
192 #define U2DMACMDR0	(0x120C)		/* U2DMA Command Address Register - Channel 0 */
193 #define U2DMACMDR(x)	(0x120C + (x) * 0x10)	/* U2DMA Command Address Register - Channel x */
199 #define U2DMACMDR_LEN		(0x07ff)	/* length mask (max = 2K - 1) */