Lines Matching +full:0 +full:x03c00000
28 #define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
29 #define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
30 #define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
31 #define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
38 #define IDP_COREVOLT_VIRT (0xf0000000)
44 #if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
59 #define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
60 #define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
61 #define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
62 #define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
63 #define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
64 #define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
65 #define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
66 #define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
67 #define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
68 #define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
69 #define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
70 #define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
71 #define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
72 #define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
74 #define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
75 #define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
76 #define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
77 #define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
107 #define PCC0_PWR0 (1 << 0)
119 #define PCC0_ENABLE (1 << 0)
130 #define PCC_VS1 (1 << 0)
158 /* leds 0 = ON */
168 #define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
169 #define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
192 inputs = (IDP_CPLD_KB_ROW & 0x7f);\