46 static void __iomem *avic_base;  variable
59 		irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);  in avic_set_irq_fiq()
60 		imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);  in avic_set_irq_fiq()
63 		irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);  in avic_set_irq_fiq()
64 		imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);  in avic_set_irq_fiq()
87 	avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);  in avic_irq_suspend()
88 	imx_writel(gc->wake_active, avic_base + ct->regs.mask);  in avic_irq_suspend()
109 	imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);  in avic_irq_resume()
129 	gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,  in avic_init_gc()
152 		nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;  in avic_handle_irq()
171 	avic_base = irqbase;  in mxc_init_irq()
188 	imx_writel(0, avic_base + AVIC_INTCNTL);  in mxc_init_irq()
189 	imx_writel(0x1f, avic_base + AVIC_NIMASK);  in mxc_init_irq()
192 	imx_writel(0, avic_base + AVIC_INTENABLEH);  in mxc_init_irq()
193 	imx_writel(0, avic_base + AVIC_INTENABLEL);  in mxc_init_irq()
196 	imx_writel(0, avic_base + AVIC_INTTYPEH);  in mxc_init_irq()
197 	imx_writel(0, avic_base + AVIC_INTTYPEL);  in mxc_init_irq()
212 		imx_writel(0, avic_base + AVIC_NIPRIORITY(i));  in mxc_init_irq()