Lines Matching +full:0 +full:x10040000
18 reg = <0xC0000000 0x40000000>;
28 reg = <0x10000000 0x40000>;
34 reg = <0x10040000 0x1000>;
40 reg = <0x10041000 0x1000>;
46 reg = <0x10042000 0x4000>;
52 reg = <0x30000000 0x40000>;
58 reg = <0x38000000 0x10000>;
81 adc1: adc@0 {
83 st,adc-channels = <0>;
96 pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
114 pinctrl-0 = <ðernet0_rmii_pins_a>;
124 #size-cells = <0>;
145 pinctrl-0 = <&i2c4_pins_a>;
155 reg = <0x32>;
160 reg = <0x33>;
161 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
181 regulator-initial-mode = <0>;
190 regulator-initial-mode = <0>;
200 regulator-initial-mode = <0>;
210 regulator-initial-mode = <0>;
218 interrupts = <IT_CURLIM_LDO1 0>;
225 interrupts = <IT_CURLIM_LDO2 0>;
238 interrupts = <IT_CURLIM_LDO4 0>;
245 interrupts = <IT_CURLIM_LDO5 0>;
253 interrupts = <IT_CURLIM_LDO6 0>;
263 interrupts = <IT_OCP_BOOST 0>;
268 interrupts = <IT_OCP_OTG 0>;
273 interrupts = <IT_OCP_SWOUT 0>;
280 interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
294 reg = <0x49>;
301 reg = <0x50>;
318 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
332 pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
334 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
336 #size-cells = <0>;
339 flash0: flash@0 {
341 reg = <0>;
359 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
374 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
390 pinctrl-0 = <&sdmmc3_b4_pins_a>;
404 pinctrl-0 = <&uart4_pins_a>;