Lines Matching +full:0 +full:x6000000
16 usb2_picophy1: phy2@0 {
18 reg = <0 0>;
19 #phy-cells = <0>;
20 st,syscfg = <&syscfg_core 0xf8 0xf4>;
28 usb2_picophy2: phy3@0 {
30 reg = <0 0>;
31 #phy-cells = <0>;
32 st,syscfg = <&syscfg_core 0xfc 0xf4>;
42 reg = <0x9a03c00 0x100>;
57 reg = <0x9a03e00 0x100>;
60 pinctrl-0 = <&pinctrl_usb0>;
74 reg = <0x9a83c00 0x100>;
89 reg = <0x9a83e00 0x100>;
92 pinctrl-0 = <&pinctrl_usb1>;
104 sti-display-subsystem@0 {
109 reg = <0 0>;
110 assigned-clocks = <&clk_s_d2_quadfs 0>,
112 <&clk_s_c0_pll1 0>,
122 assigned-clock-parents = <0>,
123 <0>,
124 <0>,
125 <&clk_s_c0_pll1 0>,
126 <&clk_s_c0_pll1 0>,
127 <&clk_s_d2_quadfs 0>,
129 <&clk_s_d2_quadfs 0>,
130 <&clk_s_d2_quadfs 0>,
131 <&clk_s_d2_quadfs 0>,
132 <&clk_s_d2_quadfs 0>;
136 <0>,
144 reg = <0x9d11000 0x1000>;
165 <&clk_s_d2_quadfs 0>,
176 reg = <0x8d08000 0x1000>;
189 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
191 <&clk_s_d2_quadfs 0>,
192 <&clk_s_d0_quadfs 0>,
193 <&clk_s_d2_quadfs 0>,
194 <&clk_s_d2_quadfs 0>;
199 reg = <0x8d04000 0x1000>;
201 #sound-dai-cells = <0>;
215 <&clk_s_d2_quadfs 0>,
227 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
235 <&clk_s_d2_quadfs 0>,
241 reg = <0x9C00000 0x100000>;
253 reg = <0x9f10000 0x1000>;
261 reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
271 reg = <0x91a0000 0x28>;
277 delta0@0 {
289 reg = <0x94a087c 0x64>;
295 pinctrl-0 = <&pinctrl_cec0_default>;