Lines Matching +full:0 +full:x03c00000
25 reg = <0x48000000 0x03c00000>;
36 reg = <0xc0011000 0x1000>;
38 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
51 clock-type = <0>; /* Slow */
52 clock-id = <0>;
56 #clock-cells = <0>;
58 clock-type = <0>; /* Slow */
63 #clock-cells = <0>;
65 clock-type = <0>; /* Slow */
70 #clock-cells = <0>;
72 clock-type = <0>; /* Slow */
77 #clock-cells = <0>;
79 clock-type = <0>; /* Slow */
84 #clock-cells = <0>;
86 clock-type = <0>; /* Slow */
91 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #clock-cells = <0>;
110 #clock-cells = <0>;
117 #clock-cells = <0>;
124 #clock-cells = <0>;
132 #clock-cells = <0>;
139 #clock-cells = <0>;
146 #clock-cells = <0>;
153 #clock-cells = <0>;
160 #clock-cells = <0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
182 #clock-cells = <0>;
185 clock-id = <0>;
189 #clock-cells = <0>;
196 #clock-cells = <0>;
203 #clock-cells = <0>;
210 #clock-cells = <0>;
215 #clock-cells = <0>;
225 reg = <0xc0014000 0x1000>;
233 reg = <0xc0016000 0x1000>;
235 interrupts = <0 1 2 18 21 22 23>;
247 reg = <0xc0011000 0x1000>;
252 reg = <0xc0012000 0x1000>;
260 reg = <0xc0017000 0x1000>;
268 reg = <0xc0020000 0x1000>;
281 reg = <0x9f800000 0x1000>, /* FSMC Register*/
282 <0x80000000 0x4000>, /* NAND Base DATA */
283 <0x80020000 0x4000>, /* NAND Base ADDR */
284 <0x80010000 0x4000>; /* NAND Base CMD */
289 partition@0 {
291 reg = <0x0 0x20000>;
295 reg = <0x20000 0x7e0000>;
299 reg = <0x800000 0xf800000>;
305 reg = <0xc0004000 0x1000>;
310 #size-cells = <0>;
313 reg = <0x48>;
315 interrupts = <0>; /* EXT0 IRQ */
373 reg = <0xc0005000 0x1000>;
378 #size-cells = <0>;
380 reg = <0x10>;
383 reg = <0x5d>;
397 reg = <0xa0001000 0x20>;
404 reg = <0xa0002000 0x20>;
409 reg = <0xc0013000 0x1000>;
420 reg = <0xc0007000 0x1000>;
429 reg = <0xc0001000 0x1000>;
438 cd-gpios = <&gpio 12 0x4>;
447 reg = <0xc0006000 0x1000>;
456 #size-cells = <0>;