Lines Matching +full:lvds +full:- +full:decoder
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/reset/rk628-rgu.h>
5 #include <dt-bindings/clock/rk628-cgu.h>
8 rk628_xin_osc0_func: rk628-xin-osc0-func {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <24000000>;
12 clock-output-names = "rk628_xin_osc0_func";
15 rk628_xin_osc0_half: rk628-xin-osc0-half {
16 compatible = "fixed-factor-clock";
17 #clock-cells = <0>;
19 clock-mult = <1>;
20 clock-div = <2>;
21 clock-output-names = "rk628_xin_osc0_half";
29 compatible = "rockchip,rk628-cru";
30 #clock-cells = <1>;
31 #reset-cells = <1>;
36 compatible = "rockchip,rk628-efuse";
38 clock-names = "pclk";
40 #phy-cells = <0>;
45 compatible = "rockchip,rk628-pinctrl";
48 rk628_gpio0: rk628-gpio0 {
50 clock-names = "pclk";
52 gpio-controller;
53 #gpio-cells = <2>;
54 interrupt-controller;
55 #interrupt-cells = <2>;
58 rk628_gpio1: rk628-gpio1 {
60 clock-names = "pclk";
62 gpio-controller;
63 #gpio-cells = <2>;
64 interrupt-controller;
65 #interrupt-cells = <2>;
68 rk628_gpio2: rk628-gpio2 {
70 clock-names = "pclk";
72 gpio-controller;
73 #gpio-cells = <2>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
78 rk628_gpio3: rk628-gpio3 {
80 clock-names = "pclk";
82 gpio-controller;
83 #gpio-cells = <2>;
84 interrupt-controller;
85 #interrupt-cells = <2>;
98 rk628_hpd_in_pins: hpd-in {
103 rk628_ddc_tx_pins: ddc-tx {
109 rk628_cec_tx_pins: cec-tx {
114 rk628_test_clkout_pins: test-clkout {
129 rk628_hpdm0_out_pins: hpdm0-out {
134 rk628_ddcm0_rx_pins: ddcm0-rx {
175 drive-strength = <1>;
178 rk628_hpdm1_out: hpdm1-out {
183 rk628_ddcm1_rx_pins: ddcm1-rx {
189 rk628_cecm1_rx_pins: cecm1-rx {
194 rk628_gvi_hpd_pins: gvi-hpd {
199 rk628_gvi_lock_pins: gvi-lock {
204 rk628_hdmirx_cec0: hdmirx-cec0 {
209 rk628_hdmirx_cec1: hdmirx-cec1 {
214 rk628_rxddc_input0: rxddc-input0 {
220 rk628_rxddc_input1: rxddc-input1 {
226 rk628_i2sm0_input: i2sm0-input {
233 rk628_i2sm1_input: i2sm1-input {
242 compatible = "rockchip,rk628-combtxphy";
244 clock-names = "pclk", "ref_clk";
246 #phy-cells = <0>;
251 compatible = "rockchip,rk628-combrxphy";
253 clock-names = "pclk";
255 #phy-cells = <0>;
260 compatible = "rockchip,rk628-dsi0";
263 clock-names = "pclk", "cfg";
266 #address-cells = <1>;
267 #size-cells = <0>;
272 compatible = "rockchip,rk628-dsi1";
275 clock-names = "pclk", "cfg";
278 #address-cells = <1>;
279 #size-cells = <0>;
283 rk628_lvds: lvds {
284 compatible = "rockchip,rk628-lvds";
290 compatible = "rockchip,rk628-gvi";
292 clock-names = "pclk";
298 rk628_rgb_tx: rgb-tx {
299 compatible = "rockchip,rk628-rgb-tx";
303 rk628_yuv_rx: yuv-rx {
304 compatible = "rockchip,rk628-yuv-rx";
308 rk628_yuv_tx: yuv-tx {
309 compatible = "rockchip,rk628-yuv-tx";
313 rk628_bt1120_rx: bt1120-rx {
314 compatible = "rockchip,rk628-bt1120-rx";
316 clock-names = "bt1120dec";
321 rk628_bt1120_tx: bt1120-tx {
322 compatible = "rockchip,rk628-bt1120-tx";
326 rk628_post_process: post-process {
327 compatible = "rockchip,rk628-post-process";
330 clock-names = "sclk_vop", "rx_read";
334 reset-names = "decoder", "clk_rx", "vop";
339 compatible = "rockchip,rk628-hdmi";
342 clock-names = "pclk", "dclk";
343 pinctrl-names = "default";
344 pinctrl-0 = <&rk628_hpd_in_pins &rk628_ddc_tx_pins &rk628_i2sm0_pins>;
345 #sound-dai-cells = <0>;
350 compatible = "rockchip,rk628-hdmirx";
355 clock-names = "pclk", "cec", "audio", "imodet";
358 reset-names = "hdmirx", "hdmirx_pon";
364 compatible = "rockchip,rk628-csi";
373 clock-names = "hdmirx", "imodet", "hdmirx_aud", "hdmirx_cec",
375 assigned-clocks = <&rk628_cru CGU_CLK_TESTOUT>;
376 assigned-clock-parents = <&rk628_cru CGU_CLK_HDMIRX_AUD>;
383 reset-names = "hdmirx", "hdmirx_pon", "decoder", "clk_rx",
386 phy-names = "combrxphy", "combtxphy";
387 pinctrl-names = "default";
388 …pinctrl-0 = <&rk628_hpdm0_out_pins &rk628_ddcm0_rx_pins &rk628_i2sm0_pins &rk628_test_clkout_pins>;