boot/dts/rk3xxx.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 	#address-cells = <1>;
13 	#size-cells = <1>;
15 	interrupt-parent = <&gic>;
36 		compatible = "simple-bus";
37 		#address-cells = <1>;
38 		#size-cells = <1>;
41 		dmac1_s: dma-controller@20018000 {
46 			#dma-cells = <1>;
47 			arm,pl330-broken-no-flushp;
48 			arm,pl330-periph-burst;
50 			clock-names = "apb_pclk";
53 		dmac1_ns: dma-controller@2001c000 {
58 			#dma-cells = <1>;
59 			arm,pl330-broken-no-flushp;
60 			arm,pl330-periph-burst;
62 			clock-names = "apb_pclk";
66 		dmac2: dma-controller@20078000 {
71 			#dma-cells = <1>;
72 			arm,pl330-broken-no-flushp;
73 			arm,pl330-periph-burst;
75 			clock-names = "apb_pclk";
80 		compatible = "fixed-clock";
81 		clock-frequency = <24000000>;
82 		#clock-cells = <0>;
83 		clock-output-names = "xin24m";
87 		compatible = "arm,mali-400";
90 		clock-names = "bus", "core";
91 		assigned-clocks = <&cru ACLK_GPU>;
92 		assigned-clock-rates = <100000000>;
97 	L2: cache-controller@10138000 {
98 		compatible = "arm,pl310-cache";
100 		cache-unified;
101 		cache-level = <2>;
105 		compatible = "arm,cortex-a9-scu";
109 	global_timer: global-timer@1013c200 {
110 		compatible = "arm,cortex-a9-global-timer";
116 		 * on Rockchip rk3066a/rk3188 are quite unstable because their rates
119 		 * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
123 	local_timer: local-timer@1013c600 {
124 		compatible = "arm,cortex-a9-twd-timer";
130 	gic: interrupt-controller@1013d000 {
131 		compatible = "arm,cortex-a9-gic";
132 		interrupt-controller;
133 		#interrupt-cells = <3>;
139 		compatible = "snps,dw-apb-uart";
142 		reg-shift = <2>;
143 		reg-io-width = <1>;
144 		clock-names = "baudclk", "apb_pclk";
150 		compatible = "snps,dw-apb-uart";
153 		reg-shift = <2>;
154 		reg-io-width = <1>;
155 		clock-names = "baudclk", "apb_pclk";
201 		compatible = "rockchip,rk3066-usb", "snps,dwc2";
205 		clock-names = "otg";
207 		g-np-tx-fifo-size = <16>;
208 		g-rx-fifo-size = <280>;
209 		g-tx-fifo-size = <256 128 128 64 32 16>;
211 		phy-names = "usb2-phy";
220 		clock-names = "otg";
223 		phy-names = "usb2-phy";
228 		compatible = "snps,arc-emac";
231 		#address-cells = <1>;
232 		#size-cells = <0>;
237 		clock-names = "hclk", "macref";
238 		max-speed = <100>;
239 		phy-mode = "rmii";
245 		compatible = "rockchip,rk2928-dw-mshc";
249 		clock-names = "biu", "ciu";
251 		dma-names = "rx-tx";
252 		fifo-depth = <256>;
254 		reset-names = "reset";
259 		compatible = "rockchip,rk2928-dw-mshc";
263 		clock-names = "biu", "ciu";
265 		dma-names = "rx-tx";
266 		fifo-depth = <256>;
268 		reset-names = "reset";
273 		compatible = "rockchip,rk2928-dw-mshc";
277 		clock-names = "biu", "ciu";
279 		dma-names = "rx-tx";
280 		fifo-depth = <256>;
282 		reset-names = "reset";
287 		compatible = "rockchip,rk-nandc";
292 		clock-names = "hclk_nandc";
297 		compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
300 		reboot-mode {
301 			compatible = "syscon-reboot-mode";
303 			mode-normal = <BOOT_NORMAL>;
304 			mode-recovery = <BOOT_RECOVERY>;
305 			mode-bootloader = <BOOT_FASTBOOT>;
306 			mode-loader = <BOOT_BL_DOWNLOAD>;
307 			mode-ums = <BOOT_UMS>;
316 	i2c0: i2c@2002d000 {
317 		compatible = "rockchip,rk3066-i2c";
320 		#address-cells = <1>;
321 		#size-cells = <0>;
325 		clock-names = "i2c";
331 	i2c1: i2c@2002f000 {
332 		compatible = "rockchip,rk3066-i2c";
335 		#address-cells = <1>;
336 		#size-cells = <0>;
341 		clock-names = "i2c";
347 		compatible = "rockchip,rk2928-pwm";
349 		#pwm-cells = <2>;
355 		compatible = "rockchip,rk2928-pwm";
357 		#pwm-cells = <2>;
363 		compatible = "snps,dw-wdt";
371 		compatible = "rockchip,rk2928-pwm";
373 		#pwm-cells = <2>;
379 		compatible = "rockchip,rk2928-pwm";
381 		#pwm-cells = <2>;
386 	i2c2: i2c@20056000 {
387 		compatible = "rockchip,rk3066-i2c";
390 		#address-cells = <1>;
391 		#size-cells = <0>;
396 		clock-names = "i2c";
401 	i2c3: i2c@2005a000 {
402 		compatible = "rockchip,rk3066-i2c";
405 		#address-cells = <1>;
406 		#size-cells = <0>;
411 		clock-names = "i2c";
416 	i2c4: i2c@2005e000 {
417 		compatible = "rockchip,rk3066-i2c";
420 		#address-cells = <1>;
421 		#size-cells = <0>;
426 		clock-names = "i2c";
432 		compatible = "snps,dw-apb-uart";
435 		reg-shift = <2>;
436 		reg-io-width = <1>;
437 		clock-names = "baudclk", "apb_pclk";
443 		compatible = "snps,dw-apb-uart";
446 		reg-shift = <2>;
447 		reg-io-width = <1>;
448 		clock-names = "baudclk", "apb_pclk";
457 		#io-channel-cells = <1>;
459 		clock-names = "saradc", "apb_pclk";
461 		reset-names = "saradc-apb";
466 		compatible = "rockchip,rk3066-spi";
468 		clock-names = "spiclk", "apb_pclk";
471 		#address-cells = <1>;
472 		#size-cells = <0>;
474 		dma-names = "tx", "rx";
479 		compatible = "rockchip,rk3066-spi";
481 		clock-names = "spiclk", "apb_pclk";
484 		#address-cells = <1>;
485 		#size-cells = <0>;
487 		dma-names = "tx", "rx";