Lines Matching +full:0 +full:x2002d000

43 			reg = <0x20018000 0x4000>;
44 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
55 reg = <0x2001c000 0x4000>;
56 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
68 reg = <0x20078000 0x4000>;
82 #clock-cells = <0>;
88 reg = <0x10090000 0x10000>;
99 reg = <0x10138000 0x1000>;
106 reg = <0x1013c000 0x100>;
111 reg = <0x1013c200 0x20>;
125 reg = <0x1013c600 0x20>;
134 reg = <0x1013d000 0x1000>,
135 <0x1013c100 0x0100>;
140 reg = <0x10124000 0x400>;
151 reg = <0x10126000 0x400>;
162 reg = <0x1012d000 0x20>;
167 reg = <0x1012e000 0x20>;
172 reg = <0x1012f000 0x20>;
177 reg = <0x1012f080 0x20>;
182 reg = <0x1012f100 0x20>;
187 reg = <0x1012f180 0x20>;
192 reg = <0x1012f200 0x20>;
197 reg = <0x1012f280 0x20>;
202 reg = <0x10180000 0x40000>;
217 reg = <0x101c0000 0x40000>;
229 reg = <0x10204000 0x3c>;
232 #size-cells = <0>;
246 reg = <0x10214000 0x1000>;
260 reg = <0x10218000 0x1000>;
274 reg = <0x1021c000 0x1000>;
288 reg = <0x10500000 0x4000>;
290 nandc_id = <0>;
298 reg = <0x20004000 0x100>;
302 offset = <0x40>;
313 reg = <0x20008000 0x200>;
318 reg = <0x2002d000 0x1000>;
321 #size-cells = <0>;
333 reg = <0x2002f000 0x1000>;
336 #size-cells = <0>;
348 reg = <0x20030000 0x10>;
356 reg = <0x20030010 0x10>;
364 reg = <0x2004c000 0x100>;
372 reg = <0x20050020 0x10>;
380 reg = <0x20050030 0x10>;
388 reg = <0x20056000 0x1000>;
391 #size-cells = <0>;
403 reg = <0x2005a000 0x1000>;
406 #size-cells = <0>;
418 reg = <0x2005e000 0x1000>;
421 #size-cells = <0>;
433 reg = <0x20064000 0x400>;
444 reg = <0x20068000 0x400>;
455 reg = <0x2006c000 0x100>;
470 reg = <0x20070000 0x1000>;
472 #size-cells = <0>;
483 reg = <0x20074000 0x1000>;
485 #size-cells = <0>;