Lines Matching +full:0 +full:xffa30000
70 #size-cells = <0>;
77 reg = <0x500>;
89 reg = <0x501>;
101 reg = <0x502>;
113 reg = <0x503>;
138 0 17
144 0 15300 0
151 rockchip,pvtm-ch = <0 0>;
269 reg = <0x0 0xff250000 0x0 0x4000>;
281 reg = <0x0 0xff600000 0x0 0x4000>;
282 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
294 reg = <0x0 0xffb20000 0x0 0x4000>;
295 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
318 * The rk3288 cannot use the memory area above 0xfe000000
328 reg = <0x0 0xfe000000 0x0 0x1000000>;
336 #clock-cells = <0>;
361 fifo-depth = <0x100>;
363 reg = <0x0 0xff0c0000 0x0 0x4000>;
375 fifo-depth = <0x100>;
377 reg = <0x0 0xff0d0000 0x0 0x4000>;
389 fifo-depth = <0x100>;
391 reg = <0x0 0xff0e0000 0x0 0x4000>;
403 fifo-depth = <0x100>;
405 reg = <0x0 0xff0f0000 0x0 0x4000>;
413 reg = <0x0 0xff100000 0x0 0x100>;
431 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
432 reg = <0x0 0xff110000 0x0 0x1000>;
434 #size-cells = <0>;
446 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
447 reg = <0x0 0xff120000 0x0 0x1000>;
449 #size-cells = <0>;
461 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
462 reg = <0x0 0xff130000 0x0 0x1000>;
464 #size-cells = <0>;
470 reg = <0x0 0xff650000 0x0 0x1000>;
473 #size-cells = <0>;
477 pinctrl-0 = <&i2c0_xfer>;
483 reg = <0x0 0xff140000 0x0 0x1000>;
486 #size-cells = <0>;
490 pinctrl-0 = <&i2c1_xfer>;
496 reg = <0x0 0xff150000 0x0 0x1000>;
499 #size-cells = <0>;
503 pinctrl-0 = <&i2c3_xfer>;
509 reg = <0x0 0xff160000 0x0 0x1000>;
512 #size-cells = <0>;
516 pinctrl-0 = <&i2c4_xfer>;
522 reg = <0x0 0xff170000 0x0 0x1000>;
525 #size-cells = <0>;
529 pinctrl-0 = <&i2c5_xfer>;
535 reg = <0x0 0xff180000 0x0 0x100>;
544 pinctrl-0 = <&uart0_xfer>;
550 reg = <0x0 0xff190000 0x0 0x100>;
559 pinctrl-0 = <&uart1_xfer>;
565 reg = <0x0 0xff690000 0x0 0x100>;
572 pinctrl-0 = <&uart2_xfer>;
578 reg = <0x0 0xff1b0000 0x0 0x100>;
587 pinctrl-0 = <&uart3_xfer>;
593 reg = <0x0 0xff1c0000 0x0 0x100>;
602 pinctrl-0 = <&uart4_xfer>;
611 thermal-sensors = <&tsadc 0>;
689 reg = <0x0 0xff280000 0x0 0x100>;
698 pinctrl-0 = <&otp_pin>;
708 reg = <0x0 0xff290000 0x0 0x10000>;
728 reg = <0x0 0xff500000 0x0 0x100>;
740 reg = <0x0 0xff520000 0x0 0x100>;
752 reg = <0x0 0xff540000 0x0 0x40000>;
766 reg = <0x0 0xff580000 0x0 0x40000>;
781 reg = <0x0 0xff5c0000 0x0 0x100>;
789 reg = <0x0 0xff660000 0x0 0x1000>;
792 #size-cells = <0>;
796 pinctrl-0 = <&i2c2_xfer>;
802 reg = <0x0 0xff680000 0x0 0x10>;
805 pinctrl-0 = <&pwm0_pin>;
813 reg = <0x0 0xff680010 0x0 0x10>;
816 pinctrl-0 = <&pwm1_pin>;
824 reg = <0x0 0xff680020 0x0 0x10>;
827 pinctrl-0 = <&pwm2_pin>;
835 reg = <0x0 0xff680030 0x0 0x10>;
838 pinctrl-0 = <&pwm3_pin>;
846 reg = <0x0 0xff6b0000 0x0 0x20>;
854 reg = <0x0 0xff700000 0x0 0x18000>;
857 ranges = <0 0x0 0xff700000 0x18000>;
858 smp-sram@0 {
860 reg = <0x00 0x10>;
866 reg = <0x0 0xff720000 0x0 0x1000>;
871 reg = <0x0 0xff730000 0x0 0x100>;
877 #size-cells = <0>;
983 offset = <0x94>;
994 reg = <0x0 0xff740000 0x0 0x1000>;
999 reg = <0x0 0xff760000 0x0 0x1000>;
1017 reg = <0x0 0xff770000 0x0 0x1000>;
1023 #phy-cells = <0>;
1047 #size-cells = <0>;
1049 port@0 {
1050 reg = <0>;
1052 #size-cells = <0>;
1054 lvds_in_vopb: endpoint@0 {
1055 reg = <0>;
1070 pinctrl-0 = <&lcdc_rgb_pins>;
1078 #size-cells = <0>;
1080 port@0 {
1081 reg = <0>;
1083 #size-cells = <0>;
1085 rgb_in_vopb: endpoint@0 {
1086 reg = <0>;
1101 #size-cells = <0>;
1105 #phy-cells = <0>;
1106 reg = <0x320>;
1109 #clock-cells = <0>;
1117 #phy-cells = <0>;
1118 reg = <0x334>;
1121 #clock-cells = <0>;
1127 #phy-cells = <0>;
1128 reg = <0x348>;
1131 #clock-cells = <0>;
1140 #size-cells = <0>;
1143 pvtm@0 {
1144 reg = <0>;
1162 reg = <0x0 0xff800000 0x0 0x100>;
1170 reg = <0x0 0xff880000 0x0 0x10000>;
1171 #sound-dai-cells = <0>;
1178 pinctrl-0 = <&spdif_tx>;
1185 reg = <0x0 0xff890000 0x0 0x10000>;
1186 #sound-dai-cells = <0>;
1192 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1195 pinctrl-0 = <&i2s0_bus>;
1205 reg = <0x0 0xff8a0000 0x0 0x4000>;
1215 reg = <0x0 0xff8a0000 0x0 0x4000>;
1227 reg = <0x0 0xff8b0000 0x0 0x10000>;
1228 #sound-dai-cells = <0>;
1235 pinctrl-0 = <&spdif_tx>;
1244 reg = <0x0 0xff900000 0x0 0x800>;
1256 reg = <0x0 0xff900800 0x0 0x40>;
1261 #iommu-cells = <0>;
1267 reg = <0x0 0xff910000 0x0 0x4000>;
1284 pinctrl-0 = <&isp_mipi>;
1296 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1307 reg = <0x0 0xff910000 0x0 0x4000>;
1325 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1330 #iommu-cells = <0>;
1337 reg = <0x0 0xff920000 0x0 0x180>;
1349 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1362 #size-cells = <0>;
1364 vopb_out_hdmi: endpoint@0 {
1365 reg = <0>;
1398 reg = <0x0 0xff930300 0x0 0x100>;
1404 #iommu-cells = <0>;
1411 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1424 #size-cells = <0>;
1426 vopl_out_hdmi: endpoint@0 {
1427 reg = <0>;
1460 reg = <0x0 0xff940300 0x0 0x100>;
1466 #iommu-cells = <0>;
1473 reg = <0x0 0xff950000 0x0 0x400>;
1482 pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
1491 reg = <0x0 0xff960000 0x0 0x4000>;
1500 #size-cells = <0>;
1506 #size-cells = <0>;
1507 dsi0_in_vopb: endpoint@0 {
1508 reg = <0>;
1521 reg = <0x0 0xff964000 0x0 0x4000>;
1530 #size-cells = <0>;
1535 #size-cells = <0>;
1539 #size-cells = <0>;
1541 dsi1_in_vopb: endpoint@0 {
1542 reg = <0>;
1555 reg = <0x0 0xff96c000 0x0 0x4000>;
1561 #phy-cells = <0>;
1567 reg = <0x0 0xff970000 0x0 0x4000>;
1582 #size-cells = <0>;
1583 edp_in: port@0 {
1584 reg = <0>;
1586 #size-cells = <0>;
1587 edp_in_vopb: endpoint@0 {
1588 reg = <0>;
1601 reg = <0x0 0xff980000 0x0 0x20000>;
1603 #sound-dai-cells = <0>;
1609 pinctrl-0 = <&hdmi_ddc>;
1618 #size-cells = <0>;
1619 hdmi_in_vopb: endpoint@0 {
1620 reg = <0>;
1633 reg = <0x0 0xff9a0000 0x0 0x800>;
1653 reg = <0x0 0xff9a0000 0x0 0x400>;
1665 rockchip,taskqueue-node = <0>;
1666 rockchip,resetgroup-node = <0>;
1672 reg = <0x0 0xff9a0400 0x0 0x400>;
1677 rockchip,normal-rates = <300000000>, <0>;
1678 rockchip,advanced-rates = <600000000>, <0>;
1686 rockchip,taskqueue-node = <0>;
1687 rockchip,resetgroup-node = <0>;
1693 reg = <0x0 0xff9a0800 0x0 0x100>;
1698 #iommu-cells = <0>;
1705 reg = <0x0 0xff9c0000 0x0 0x400>;
1712 rockchip,normal-rates = <300000000>, <0>, <200000000>,
1714 rockchip,advanced-rates = <500000000>, <0>, <400000000>,
1739 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1745 #iommu-cells = <0>;
1753 reg = <0x0 0xffa30000 0x0 0x10000>;
1784 0 55
1814 reg = <0x0 0xffaa0000 0x0 0x20>;
1819 reg = <0x0 0xffaa0080 0x0 0x20>;
1824 reg = <0x0 0xffad0000 0x0 0x20>;
1829 reg = <0x0 0xffad0100 0x0 0x20>;
1834 reg = <0x0 0xffad0180 0x0 0x20>;
1839 reg = <0x0 0xffad0400 0x0 0x20>;
1844 reg = <0x0 0xffad0480 0x0 0x20>;
1849 reg = <0x0 0xffad0500 0x0 0x20>;
1854 reg = <0x0 0xffad0800 0x0 0x20>;
1859 reg = <0x0 0xffad0880 0x0 0x20>;
1864 reg = <0x0 0xffad0900 0x0 0x20>;
1869 reg = <0x0 0xffae0000 0x0 0x20>;
1874 reg = <0x0 0xffaf0000 0x0 0x20>;
1879 reg = <0x0 0xffaf0080 0x0 0x20>;
1884 reg = <0x0 0xffb40000 0x0 0x20>;
1891 reg = <0x5 0x1>;
1895 reg = <0x5 0x1>;
1899 reg = <0x6 0x1>;
1900 bits = <0 4>;
1903 reg = <0x07 0x10>;
1906 reg = <0x17 0x1>;
1909 reg = <0x1c 0x1>;
1913 reg = <0x1d 0x1>;
1922 #address-cells = <0>;
1924 reg = <0x0 0xffc01000 0x0 0x1000>,
1925 <0x0 0xffc02000 0x0 0x2000>,
1926 <0x0 0xffc04000 0x0 0x2000>,
1927 <0x0 0xffc06000 0x0 0x2000>;
1928 interrupts = <GIC_PPI 9 0xf04>;
1939 (0
1948 (0
1953 (0
1969 reg = <0x0 0xff750000 0x0 0x100>;
1982 reg = <0x0 0xff780000 0x0 0x100>;
1995 reg = <0x0 0xff790000 0x0 0x100>;
2008 reg = <0x0 0xff7a0000 0x0 0x100>;
2021 reg = <0x0 0xff7b0000 0x0 0x100>;
2034 reg = <0x0 0xff7c0000 0x0 0x100>;
2047 reg = <0x0 0xff7d0000 0x0 0x100>;
2060 reg = <0x0 0xff7e0000 0x0 0x100>;
2073 reg = <0x0 0xff7f0000 0x0 0x100>;