Lines Matching +full:a +full:- +full:facing
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "rk3288-evb-android-rk808-edp.dtsi"
12 compatible = "rockchip,rk3288-evb-android-rk808-edp", "rockchip,rk3288";
14 …t8250,mmio32,0xff690000 vmalloc=496M console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymo…
20 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
21 rockchip,normal-rates = <300000000>, <0>, <200000000>, <200000000>;
22 rockchip,advanced-rates = <600000000>, <0>, <500000000>, <500000000>;
28 dvp-supply = <&vcc_18>;
39 #address-cells = <1>;
40 #size-cells = <0>;
43 rockchip,camera-module-index = <0>;
44 rockchip,camera-module-facing = "back";
45 enable-gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
46 strobe-gpio = <&gpio7 RK_PB5 GPIO_ACTIVE_HIGH>;
50 led-max-microamp = <299200>;
51 flash-max-microamp = <1122000>;
52 flash-max-timeout-us = <1600000>;
57 led-max-microamp = <299200>;
58 flash-max-microamp = <1122000>;
59 flash-max-timeout-us = <1600000>;
67 rockchip,camera-module-index = <0>;
68 rockchip,camera-module-facing = "back";
75 clock-names = "xvclk";
76 /* avdd-supply = <>; */
77 /* dvdd-supply = <>; */
78 /* dovdd-supply = <>; */
79 /* reset-gpios = <>; */
80 pinctrl-names = "rockchip,camera_default";
81 pinctrl-0 = <&isp_mipi>;
82 power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
83 pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
84 rockchip,camera-module-index = <0>;
85 rockchip,camera-module-facing = "back";
86 rockchip,camera-module-name = "CMK-CT0116";
87 rockchip,camera-module-lens-name = "Largan-50013A1";
88 lens-focus = <&vm149c>;
89 flash-leds = <&sgm3784_led0 &sgm3784_led1>;
92 remote-endpoint = <&mipi_in_ucam0>;
93 data-lanes = <1 2>;
103 #address-cells = <1>;
104 #size-cells = <0>;
108 #address-cells = <1>;
109 #size-cells = <0>;
113 remote-endpoint = <&ov13850_out>;
114 data-lanes = <1 2>;
120 #address-cells = <1>;
121 #size-cells = <0>;
125 remote-endpoint = <&isp_mipi_in>;
134 #address-cells = <1>;
135 #size-cells = <0>;
139 remote-endpoint = <&dphy_rx_out>;
150 assigned-clocks = <&cru DCLK_VOP0>;
151 assigned-clock-parents = <&cru PLL_GPLL>;
155 assigned-clocks = <&cru DCLK_VOP1>;
156 assigned-clock-parents = <&cru PLL_CPLL>;