boot/dts/rk312x.dtsi

75 		#size-cells = <0>;
80 			reg = <0xf00>;
89 			reg = <0xf01>;
95 			reg = <0xf02>;
101 			reg = <0xf03>;
112 			14  254  0
116 			1   13   0
190 			reg = <0x20078000 0x4000>;
191 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
231 		vop-dclk-mode = <0>;
241 		auto-freq-en = <0>;
295 			thermal-sensors = <&tsadc 0>;
338 		#clock-cells = <0>;
343 		reg = <0x10090000 0x10000>;
401 		reg = <0x100a0000 0x1000>;
409 			#size-cells = <0>;
455 			offset = <0x38>;
471 		rockchip,grf-offset = <0x0144>;
472 		rockchip,grf-values = <0x04000400>, <0x04000400>;
479 		reg = <0x10104000 0x400>;
492 		rockchip,taskqueue-node = <0>;
493 		rockchip,resetgroup-node = <0>;
499 		reg = <0x10104440 0x40>, <0x10104480 0x40>;
505 		#iommu-cells = <0>;
509 	vepu: vepu@0x10106000 {
511 		reg = <0x10106000 0x400>;
521 		rockchip,taskqueue-node = <0>;
522 		rockchip,resetgroup-node = <0>;
528 		reg = <0x10106400 0x400>;
538 		rockchip,taskqueue-node = <0>;
539 		rockchip,resetgroup-node = <0>;
545 		reg = <0x10106800 0x40>;
551 		#iommu-cells = <0>;
559 		reg = <0x10108000 0x800>;
571 		reg = <0x10108800 0x40>;
577 		#iommu-cells = <0>;
583 		reg = <0x1010a000 0x200>;
597 		reg = <0x1010a000 0x200>;
615 		reg = <0x1010c000 0x1000>;
625 		reg = <0x1010e000 0x100>, <0x1010ec00 0x400>;
638 			#size-cells = <0>;
640 			vop_out_dsi: endpoint@0 {
641 				reg = <0>;
659 		reg = <0x1010e300 0x100>;
665 		#iommu-cells = <0>;
672 		reg = <0x10110000 0x4000>;
683 		#size-cells = <0>;
697 		reg = <0x1012d000 0x20>;
702 		reg = <0x1012e000 0x20>;
707 		reg = <0x1012f000 0x20>;
712 		reg = <0x1012f100 0x20>;
717 		reg = <0x1012f180 0x20>;
722 		reg = <0x1012f200 0x20>;
729 		#address-cells = <0>;
731 		reg = <0x10139000 0x1000>,
732 		      <0x1013a000 0x1000>,
733 		      <0x1013c000 0x2000>,
734 		      <0x1013e000 0x2000>;
735 		interrupts = <GIC_PPI 9 0xf04>;
741 		reg = <0x10180000 0x40000>;
757 		reg = <0x101c0000 0x20000>;
768 		reg = <0x101e0000 0x20000>;
779 		reg = <0x10200000 0x1000>;
792 		reg = <0x10204000 0x1000>;
799 		pinctrl-0 = <&spdif_tx>;
805 		reg = <0x1020c000 0x8000>;
816 		reg = <0x10220000 0x1000>;
820 		dmas = <&pdma 0>, <&pdma 1>;
829 		reg = <0x10214000 0x4000>;
832 		#size-cells = <0>;
834 		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
840 		fifo-depth = <0x100>;
847 		reg = <0x10218000 0x4000>;
850 		#size-cells = <0>;
852 		pinctrl-0 = <&sdio_pwren &sdio_cmd &sdio_clk &sdio_bus4>;
859 		fifo-depth = <0x100>;
866 		reg = <0x1021c000 0x4000>;
869 		#size-cells = <0>;
876 		fifo-depth = <0x100>;
883 		reg = <0x10500000 0x4000>;
885 		nandc_id = <0>;
893 		reg = <0x20000000 0x1000>;
909 		reg = <0x20008000 0x1000>;
921 				#size-cells = <0>;
923 				port@0 {
924 					reg = <0>;
938 			pinctrl-0 = <&lcdc_rgb_pins>;
944 				#size-cells = <0>;
946 				port@0 {
947 					reg = <0>;
958 			reg = <0x017c 0x0c>;
961 			#clock-cells = <0>;
968 				#phy-cells = <0>;
978 				#phy-cells = <0>;
988 		reg = <0x20030000 0x4000>;
1000 		reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
1005 		#clock-cells = <0>;
1009 		#phy-cells = <0>;
1015 		reg = <0x20044000 0x20>;
1023 		reg = <0x2004c000 0x100>;
1031 		reg = <0x20050000 0x10>;
1034 		pinctrl-0 = <&pwm0_pin>;
1042 		reg = <0x20050010 0x10>;
1045 		pinctrl-0 = <&pwm1_pin>;
1053 		reg = <0x20050020 0x10>;
1056 		pinctrl-0 = <&pwm2_pin>;
1064 		reg = <0x20050030 0x10>;
1067 		pinctrl-0 = <&pwm3_pin>;
1075 		reg = <0x20056000 0x1000>;
1078 		#size-cells = <0>;
1082 		pinctrl-0 = <&i2c1_xfer>;
1088 		reg = <0x2005a000 0x1000>;
1091 		#size-cells = <0>;
1095 		pinctrl-0 = <&i2c2_xfer>;
1101 		reg = <0x2005e000 0x1000>;
1104 		#size-cells = <0>;
1108 		pinctrl-0 = <&i2c3_xfer>;
1114 		reg = <0x20060000 0x100>;
1122 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
1128 		reg = <0x20064000 0x100>;
1136 		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
1142 		reg = <0x20068000 0x100>;
1150 		pinctrl-0 = <&uart2_xfer>;
1156 		reg = <0x2006c000 0x100>;
1168 		reg = <0x20072000 0x1000>;
1171 		#size-cells = <0>;
1175 		pinctrl-0 = <&i2c0_xfer>;
1181 		reg = <0x20074000 0x1000>;
1184 		pinctrl-0 = <&spi0m0_tx &spi0m0_rx &spi0m0_clk &spi0m0_cs0 &spi0m0_cs1>;
1189 		#size-cells = <0>;
1195 		reg = <0x2008c000 0x4000>;
1215 		reg = <0x20090000 0x20>;
1222 			reg = <0x7 0x10>;
1225 			reg = <0x17 0x1>;
1242 			reg = <0x2007c000 0x100>;
1255 			reg = <0x20080000 0x100>;
1268 			reg = <0x20084000 0x100>;
1281 			reg = <0x20088000 0x100>;
1346 				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1347 						<0 RK_PA1 1 &pcfg_pull_none>;
1353 				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1354 						<0 RK_PA3 1 &pcfg_pull_none>;
1367 				rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1368 						<0 RK_PA7 1 &pcfg_pull_none>;
1429 				rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1455 				rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1459 				rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1498 				rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1502 				rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1515 				rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1516 						<0 RK_PA7 2 &pcfg_pull_none>;
1520 				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
1524 				rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1530 				rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1531 						<0 RK_PB1 1 &pcfg_pull_none>,
1532 						<0 RK_PB3 1 &pcfg_pull_none>,
1533 						<0 RK_PB4 1 &pcfg_pull_none>,
1534 						<0 RK_PB5 1 &pcfg_pull_none>,
1535 						<0 RK_PB6 1 &pcfg_pull_none>;
1550 				rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
1556 				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1562 				rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1653 				rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1657 				rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1661 				rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1665 				rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;