Lines Matching +full:rk3066 +full:- +full:usb
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/power/rk3036-power.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
17 interrupt-parent = <&gic>;
37 #address-cells = <1>;
38 #size-cells = <0>;
39 enable-method = "rockchip,rk3036-smp";
43 compatible = "arm,cortex-a7";
46 operating-points-v2 = <&cpu0_opp_table>;
52 compatible = "arm,cortex-a7";
55 operating-points-v2 = <&cpu0_opp_table>;
60 compatible = "operating-points-v2";
61 opp-shared;
63 opp-408000000 {
64 opp-hz = /bits/ 64 <408000000>;
65 opp-microvolt = <1000000 1000000 1225000>;
66 clock-latency-ns = <40000>;
68 opp-600000000 {
69 opp-hz = /bits/ 64 <600000000>;
70 opp-microvolt = <1000000 1000000 1225000>;
71 clock-latency-ns = <40000>;
73 opp-816000000 {
74 opp-hz = /bits/ 64 <816000000>;
75 opp-microvolt = <1100000 1100000 1225000>;
76 clock-latency-ns = <40000>;
77 opp-suspend;
79 opp-1008000000 {
80 opp-hz = /bits/ 64 <1008000000>;
81 opp-microvolt = <1150000 1150000 1225000>;
82 clock-latency-ns = <40000>;
84 opp-1200000000 {
85 opp-hz = /bits/ 64 <1200000000>;
86 opp-microvolt = <1225000 1225000 1225000>;
87 clock-latency-ns = <40000>;
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
102 #dma-cells = <1>;
103 arm,pl330-broken-no-flushp;
104 arm,pl330-periph-burst;
106 clock-names = "apb_pclk";
110 arm-pmu {
111 compatible = "arm,cortex-a7-pmu";
114 interrupt-affinity = <&cpu0>, <&cpu1>;
117 display-subsystem {
118 compatible = "rockchip,display-subsystem";
123 compatible = "arm,psci-1.0";
128 compatible = "arm,armv7-timer";
129 arm,cpu-registers-not-fw-configured;
134 clock-frequency = <24000000>;
138 compatible = "fixed-clock";
139 clock-frequency = <24000000>;
140 clock-output-names = "xin24m";
141 #clock-cells = <0>;
145 compatible = "mmio-sram";
147 #address-cells = <1>;
148 #size-cells = <1>;
151 smp-sram@0 {
152 compatible = "rockchip,rk3066-smp-sram";
168 interrupt-names = "Mali_GP_IRQ",
174 clock-names = "clk_mali";
175 assigned-clocks = <&cru SCLK_GPU>;
176 assigned-clock-rates = <400000000>;
177 assigned-clock-parents = <&cru PLL_DPLL>;
178 power-domains = <&power RK3036_PD_GPU>;
179 operating-points-v2 = <&gpu_opp_table>;
184 compatible = "arm,mali-simple-power-model";
187 static-power = <300>;
188 dynamic-power = <396>;
189 ts = <32000 4700 (-80) 2>;
190 thermal-zone = "soc-thermal";
194 gpu_opp_table: opp-table1 {
195 compatible = "operating-points-v2";
197 opp-200000000 {
198 opp-hz = /bits/ 64 <200000000>;
199 opp-microvolt = <1000000>;
201 opp-400000000 {
202 opp-hz = /bits/ 64 <400000000>;
203 opp-microvolt = <1100000>;
207 mpp_srv: mpp-srv {
208 compatible = "rockchip,mpp-service";
209 rockchip,taskqueue-count = <1>;
210 rockchip,resetgroup-count = <1>;
212 rockchip,grf-offset = <0x0144>;
213 rockchip,grf-values = <0x0008000a>, <0x00080002>;
214 rockchip,grf-names = "grf_rkvdec", "grf_vdpu1";
219 compatible = "rockchip,vpu-decoder-rk3036";
222 interrupt-names = "irq_dec";
224 clock-names = "aclk_vcodec", "hclk_vcodec";
225 rockchip,normal-rates = <297000000>, <0>;
226 assigned-clocks = <&cru ACLK_VCODEC>;
227 assigned-clock-rates = <297000000>;
228 assigned-clock-parents = <&cru PLL_GPLL>;
230 reset-names = "shared_video_a", "shared_video_h";
232 power-domains = <&power RK3036_PD_VPU>;
234 rockchip,taskqueue-node = <0>;
235 rockchip,resetgroup-node = <0>;
243 interrupt-names = "vpu_mmu";
245 clock-names = "aclk", "iface";
246 #iommu-cells = <0>;
247 power-domains = <&power RK3036_PD_VPU>;
252 compatible = "rockchip,hevc-decoder-rk3036";
255 interrupt-names = "irq_dec";
257 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
258 rockchip,normal-rates = <297000000>, <0>, <200000000>;
259 assigned-clocks = <&cru ACLK_VCODEC>;
260 assigned-clock-rates = <297000000>;
261 assigned-clock-parents = <&cru PLL_GPLL>;
263 reset-names = "shared_video_a", "shared_video_h", "video_core";
266 rockchip,taskqueue-node = <0>;
267 rockchip,resetgroup-node = <0>;
268 power-domains = <&power RK3036_PD_VPU>;
276 interrupt-names = "hevc_mmu";
278 clock-names = "aclk", "iface";
279 #iommu-cells = <0>;
280 power-domains = <&power RK3036_PD_VPU>;
285 compatible = "rockchip,rk3036-vop";
289 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
291 reset-names = "axi", "ahb", "dclk";
296 #address-cells = <1>;
297 #size-cells = <0>;
300 remote-endpoint = <&hdmi_in_vop>;
304 remote-endpoint = <&tve_in_vop>;
310 compatible = "rockchip,rk3036-tve";
313 clock-names = "aclk";
326 #address-cells = <1>;
327 #size-cells = <0>;
330 remote-endpoint = <&vop_out_tve>;
340 interrupt-names = "vop_mmu";
342 clock-names = "aclk", "iface";
343 #iommu-cells = <0>;
352 gic: interrupt-controller@10139000 {
353 compatible = "arm,gic-400";
354 interrupt-controller;
355 #interrupt-cells = <3>;
356 #address-cells = <0>;
365 usb_otg: usb@10180000 {
366 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
371 clock-names = "otg";
373 g-np-tx-fifo-size = <16>;
374 g-rx-fifo-size = <280>;
375 g-tx-fifo-size = <256 128 128 64 32 16>;
379 usb_host: usb@101c0000 {
380 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
385 clock-names = "otg";
391 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
394 #address-cells = <1>;
395 #size-cells = <0>;
398 clock-names = "hclk", "macref", "macclk";
404 assigned-clocks = <&cru SCLK_MACPLL>;
405 assigned-clock-parents = <&cru PLL_DPLL>;
406 max-speed = <100>;
407 phy-mode = "rmii";
411 spdif_tx: spdif-tx@10204000 {
412 compatible = "rockchip,rk3066-spdif";
415 clock-names = "mclk", "hclk";
418 dma-names = "tx";
419 pinctrl-names = "default";
420 pinctrl-0 = <&spdif_out>;
421 #sound-dai-cells = <0>;
430 clock-names = "clk_sfc", "hclk_sfc";
435 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
437 clock-frequency = <37500000>;
438 max-frequency = <37500000>;
440 clock-names = "biu", "ciu";
441 fifo-depth = <0x100>;
444 reset-names = "reset";
445 no-mmc;
446 no-sdio;
451 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
453 max-frequency = <37500000>;
456 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
457 fifo-depth = <0x100>;
460 reset-names = "reset";
461 no-mmc;
462 no-sd;
467 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
470 bus-width = <8>;
471 cap-mmc-highspeed;
472 clock-frequency = <37500000>;
473 max-frequency = <37500000>;
476 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
477 rockchip,default-sample-phase = <158>;
478 disable-wp;
480 dma-names = "rx-tx";
481 fifo-depth = <0x100>;
482 non-removable;
483 no-sdio;
484 no-sd;
485 pinctrl-names = "default";
486 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
488 reset-names = "reset";
493 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
496 clock-names = "i2s_clk", "i2s_hclk";
498 assigned-clocks = <&cru SCLK_I2S_PRE>;
499 assigned-clock-parents = <&cru SCLK_I2S_FRAC>;
501 dma-names = "tx", "rx";
503 reset-names = "reset-m";
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2s_mclk
511 #sound-dai-cells = <0>;
515 cru: clock-controller@20000000 {
516 compatible = "rockchip,rk3036-cru";
519 #clock-cells = <1>;
520 #reset-cells = <1>;
521 assigned-clocks = <&cru PLL_GPLL>;
522 assigned-clock-rates = <594000000>;
526 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
528 #address-cells = <1>;
529 #size-cells = <1>;
531 reboot-mode {
532 compatible = "syscon-reboot-mode";
534 mode-normal = <BOOT_NORMAL>;
535 mode-recovery = <BOOT_RECOVERY>;
536 mode-bootloader = <BOOT_FASTBOOT>;
537 mode-loader = <BOOT_BL_DOWNLOAD>;
538 mode-ums = <BOOT_UMS>;
541 power: power-controller {
542 compatible = "rockchip,rk3036-power-controller";
543 #power-domain-cells = <1>;
544 #address-cells = <1>;
545 #size-cells = <0>;
560 usb2phy: usb2-phy@17c {
561 compatible = "rockchip,rk3036-usb2phy";
564 clock-names = "phyclk";
565 #clock-cells = <0>;
566 clock-output-names = "usb480m_phy";
569 u2phy_otg: otg-port {
570 #phy-cells = <0>;
574 interrupt-names = "otg-bvalid", "otg-id",
579 u2phy_host: host-port {
580 #phy-cells = <0>;
582 interrupt-names = "linestate";
588 acodec: acodec-ana@20030000 {
589 compatible = "rockchip,rk3036-codec";
592 clock-names = "acodec_pclk";
598 compatible = "rockchip,rk3036-inno-hdmi";
602 clock-names = "aclk", "pclk";
604 pinctrl-names = "default";
605 pinctrl-0 = <&hdmi_ctl>;
606 #address-cells = <1>;
607 #size-cells = <0>;
608 #sound-dai-cells = <0>;
612 #address-cells = <1>;
613 #size-cells = <0>;
616 remote-endpoint = <&vop_out_hdmi>;
622 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
626 clock-names = "timer", "pclk";
630 compatible = "rockchip,rk3036-wdt", "snps,dw-wdt";
637 compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
639 #pwm-cells = <3>;
641 clock-names = "pwm";
642 pinctrl-names = "active";
643 pinctrl-0 = <&pwm0_pin>;
648 compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
650 #pwm-cells = <3>;
652 clock-names = "pwm";
653 pinctrl-names = "active";
654 pinctrl-0 = <&pwm1_pin>;
659 compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
661 #pwm-cells = <3>;
663 clock-names = "pwm";
664 pinctrl-names = "active";
665 pinctrl-0 = <&pwm2_pin>;
670 compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
673 #pwm-cells = <3>;
675 clock-names = "pwm";
676 pinctrl-names = "active";
677 pinctrl-0 = <&pwm3_pin>;
682 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
685 #address-cells = <1>;
686 #size-cells = <0>;
687 clock-names = "i2c";
689 pinctrl-names = "default";
690 pinctrl-0 = <&i2c1_xfer>;
695 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
698 #address-cells = <1>;
699 #size-cells = <0>;
700 clock-names = "i2c";
702 pinctrl-names = "default";
703 pinctrl-0 = <&i2c2_xfer>;
708 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
711 reg-shift = <2>;
712 reg-io-width = <4>;
713 clock-frequency = <24000000>;
715 clock-names = "baudclk", "apb_pclk";
716 pinctrl-names = "default";
717 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
722 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
725 reg-shift = <2>;
726 reg-io-width = <4>;
727 clock-frequency = <24000000>;
729 clock-names = "baudclk", "apb_pclk";
730 pinctrl-names = "default";
731 pinctrl-0 = <&uart1_xfer>;
736 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
739 reg-shift = <2>;
740 reg-io-width = <4>;
741 clock-frequency = <24000000>;
743 clock-names = "baudclk", "apb_pclk";
744 pinctrl-names = "default";
745 pinctrl-0 = <&uart2_xfer>;
750 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
753 #address-cells = <1>;
754 #size-cells = <0>;
755 clock-names = "i2c";
757 pinctrl-names = "default";
758 pinctrl-0 = <&i2c0_xfer>;
763 compatible = "rockchip,rockchip-spi";
767 clock-names = "apb-pclk","spi_pclk";
769 dma-names = "tx", "rx";
770 pinctrl-names = "default";
771 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
772 #address-cells = <1>;
773 #size-cells = <0>;
778 compatible = "rockchip,rk3036-pinctrl";
780 #address-cells = <1>;
781 #size-cells = <1>;
785 compatible = "rockchip,gpio-bank";
788 clock-names = "bus";
791 gpio-controller;
792 #gpio-cells = <2>;
794 interrupt-controller;
795 #interrupt-cells = <2>;
799 compatible = "rockchip,gpio-bank";
802 clock-names = "bus";
805 gpio-controller;
806 #gpio-cells = <2>;
808 interrupt-controller;
809 #interrupt-cells = <2>;
813 compatible = "rockchip,gpio-bank";
816 clock-names = "bus";
819 gpio-controller;
820 #gpio-cells = <2>;
822 interrupt-controller;
823 #interrupt-cells = <2>;
827 bias-pull-pin-default;
830 pcfg_pull_none: pcfg-pull-none {
831 bias-disable;
835 pwm0_pin: pwm0-pin {
841 pwm1_pin: pwm1-pin {
847 pwm2_pin: pwm2-pin {
853 pwm3_pin: pwm3-pin {
859 sdmmc_clk: sdmmc-clk {
863 sdmmc_cmd: sdmmc-cmd {
867 sdmmc_cd: sdmmc-cd {
871 sdmmc_bus1: sdmmc-bus1 {
875 sdmmc_bus4: sdmmc-bus4 {
884 sdio_bus1: sdio-bus1 {
888 sdio_bus4: sdio-bus4 {
895 sdio_cmd: sdio-cmd {
899 sdio_clk: sdio-clk {
909 emmc_clk: emmc-clk {
913 emmc_cmd: emmc-cmd {
917 emmc_bus8: emmc-bus8 {
930 spdif_out: spdif-out {
936 emac_xfer: emac-xfer {
947 emac_mdio: emac-mdio {
954 i2c0_xfer: i2c0-xfer {
961 i2c1_xfer: i2c1-xfer {
968 i2c2_xfer: i2c2-xfer {
975 i2s_mclk: i2s-mclk {
978 i2s_sclk: i2s-sclk {
981 i2s_lrclkrx: i2s-lrclkrx {
984 i2s_lrclktx: i2s-lrclktx {
987 i2s_sdo: i2s-sdo {
990 i2s_sdi: i2s-sdi {
996 hdmi_ctl: hdmi-ctl {
1005 uart0_xfer: uart0-xfer {
1010 uart0_cts: uart0-cts {
1014 uart0_rts: uart0-rts {
1020 uart1_xfer: uart1-xfer {
1028 uart2_xfer: uart2-xfer {
1035 spi-pins {
1036 spi_txd:spi-txd {
1040 spi_rxd:spi-rxd {
1044 spi_clk:spi-clk {
1048 spi_cs0:spi-cs0 {
1053 spi_cs1:spi-cs1 {