Lines Matching +full:0 +full:x01f00000
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
113 reg = <0 0x48211000 0 0x1000>,
114 <0 0x48212000 0 0x2000>,
115 <0 0x48214000 0 0x2000>,
116 <0 0x48216000 0 0x2000>;
124 reg = <0 0x48281000 0 0x1000>;
152 ranges = <0 0 0 0xc0000000>;
153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
155 reg = <0 0x44000000 0 0x2000>,
156 <0 0x44800000 0 0x3000>,
157 <0 0x45000000 0 0x4000>;
175 reg = <0x40300000 0x20000>; /* 128k */
180 reg = <0x50000000 0x1000>;
199 reg = <0x55082000 0x4>,
200 <0x55082010 0x4>,
201 <0x55082014 0x4>;
209 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
213 ranges = <0x0 0x55082000 0x100>;
217 mmu_ipu: mmu@0 {
219 reg = <0x0 0x100>;
221 #iommu-cells = <0>;
228 ti,bootreg = <&scm_conf 0x304 0>;
230 resets = <&prm_dsp 0>;
231 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
239 reg = <0x55020000 0x10000>;
242 resets = <&prm_core 0>, <&prm_core 1>;
243 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
251 reg = <0x4e000000 0x800>;
252 interrupts = <0 113 0x4>;
261 reg = <0x4c000000 0x400>;
273 reg = <0x4d000000 0x400>;
282 reg = <0x4b501080 0x4>,
283 <0x4b501084 0x4>,
284 <0x4b501088 0x4>;
294 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
298 ranges = <0x0 0x4b501000 0x1000>;
300 aes1: aes@0 {
302 reg = <0 0xa0>;
311 reg = <0x4b701080 0x4>,
312 <0x4b701084 0x4>,
313 <0x4b701088 0x4>;
323 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
327 ranges = <0x0 0x4b701000 0x1000>;
329 aes2: aes@0 {
331 reg = <0 0xa0>;
340 reg = <0x4b100100 0x4>,
341 <0x4b100110 0x4>,
342 <0x4b100114 0x4>;
351 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
355 ranges = <0x0 0x4b100000 0x1000>;
357 sham: sham@0 {
359 reg = <0 0x300>;
367 reg = <0x4a0021e0 0xc
368 0x4a00232c 0xc
369 0x4a002380 0x2c
370 0x4a0023C0 0x3c>;
380 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
386 ports-implemented = <0x1>;
391 reg = <0x5600fe00 0x4>,
392 <0x5600fe10 0x4>;
400 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
404 ranges = <0 0x56000000 0x2000000>;
414 reg = <0x58000000 4>,
415 <0x58000014 4>;
418 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
425 ranges = <0 0x58000000 0x1000000>;
427 dss: dss@0 {
429 reg = <0 0x80>;
435 ranges = <0 0 0x1000000>;
439 reg = <0x1000 0x4>,
440 <0x1010 0x4>,
441 <0x1014 0x4>;
458 ranges = <0 0x1000 0x1000>;
460 dispc@0 {
462 reg = <0 0x1000>;
471 reg = <0x2000 0x4>,
472 <0x2010 0x4>,
473 <0x2014 0x4>;
485 ranges = <0 0x2000 0x1000>;
487 rfbi: encoder@0 {
489 reg = <0 0x100>;
498 reg = <0x4000 0x4>,
499 <0x4010 0x4>,
500 <0x4014 0x4>;
512 ranges = <0 0x4000 0x1000>;
514 dsi1: encoder@0 {
516 reg = <0 0x200>,
517 <0x200 0x40>,
518 <0x300 0x40>;
530 reg = <0x9000 0x4>,
531 <0x9010 0x4>,
532 <0x9014 0x4>;
544 ranges = <0 0x9000 0x1000>;
546 dsi2: encoder@0 {
548 reg = <0 0x200>,
549 <0x200 0x40>,
550 <0x300 0x40>;
562 reg = <0x40000 0x4>,
563 <0x40010 0x4>;
575 ranges = <0 0x40000 0x40000>;
577 hdmi: encoder@0 {
579 reg = <0 0x200>,
580 <0x200 0x80>,
581 <0x300 0x80>,
582 <0x20000 0x19000>;
599 #address-cells = <0>;
600 #size-cells = <0>;
605 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
606 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
609 ti,tranxdone-status-mask = <0x80>;
611 ti,ldovbb-override-mask = <0x400>;
613 ti,ldovbb-vset-mask = <0x1F>;
621 1060000 0 0x0 0 0x02000000 0x01F00000
622 1250000 0 0x4 0 0x02000000 0x01F00000
629 #address-cells = <0>;
630 #size-cells = <0>;
635 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
636 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
639 ti,tranxdone-status-mask = <0x80000000>;
641 ti,ldovbb-override-mask = <0x400>;
643 ti,ldovbb-vset-mask = <0x1F>;
651 1025000 0 0x0 0 0x02000000 0x01F00000
652 1120000 0 0x4 0 0x02000000 0x01F00000
671 coefficients = <0 2000>;
680 reg = <0x400 0x100>;
686 reg = <0x500 0x100>;
687 #power-domain-cells = <0>;
692 reg = <0x700 0x100>;
698 reg = <0x1200 0x100>;
704 reg = <0x1c00 0x100>;
713 timer@0 {