Lines Matching +full:0 +full:x52000000
40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
76 reg = <0x48241000 0x1000>,
77 <0x48240100 0x0100>;
83 reg = <0x48242000 0x1000>;
91 reg = <0x48240600 0x20>;
100 reg = <0x48281000 0x1000>;
135 reg = <0x44000000 0x1000>,
136 <0x44800000 0x2000>,
137 <0x45000000 0x1000>;
155 reg = <0x40304000 0xa000>; /* 40k */
160 reg = <0x50000000 0x1000>;
181 reg = <0x52000000 0x4>,
182 <0x52000010 0x4>;
194 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
198 ranges = <0 0x52000000 0x1000000>;
205 reg = <0x55082000 0x4>,
206 <0x55082010 0x4>,
207 <0x55082014 0x4>;
215 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
219 ranges = <0x0 0x55082000 0x100>;
223 mmu_ipu: mmu@0 {
225 reg = <0x0 0x100>;
227 #iommu-cells = <0>;
234 reg = <0x4012c000 0x4>,
235 <0x4012c010 0x4>;
242 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
246 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
247 <0x4902c000 0x4902c000 0x1000>; /* L3 */
254 reg = <0x4e000000 0x800>;
255 interrupts = <0 113 0x4>;
261 reg = <0x4c000000 0x100>;
273 reg = <0x4d000000 0x100>;
285 ti,bootreg = <&scm_conf 0x304 0>;
287 resets = <&prm_tesla 0>;
288 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
296 reg = <0x55020000 0x10000>;
299 resets = <&prm_core 0>, <&prm_core 1>;
300 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
308 reg = <0x4b501080 0x4>,
309 <0x4b501084 0x4>,
310 <0x4b501088 0x4>;
320 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
324 ranges = <0x0 0x4b501000 0x1000>;
326 aes1: aes@0 {
328 reg = <0 0xa0>;
337 reg = <0x4b701080 0x4>,
338 <0x4b701084 0x4>,
339 <0x4b701088 0x4>;
349 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
353 ranges = <0x0 0x4b701000 0x1000>;
355 aes2: aes@0 {
357 reg = <0 0xa0>;
366 reg = <0x4b100100 0x4>,
367 <0x4b100110 0x4>,
368 <0x4b100114 0x4>;
377 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
381 ranges = <0x0 0x4b100000 0x1000>;
383 sham: sham@0 {
385 reg = <0 0x300>;
395 #address-cells = <0>;
396 #size-cells = <0>;
397 ti,tranxdone-status-mask = <0x80>;
408 #address-cells = <0>;
409 #size-cells = <0>;
410 ti,tranxdone-status-mask = <0x80000000>;
420 reg = <0x5600fe00 0x4>,
421 <0x5600fe10 0x4>;
431 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
435 ranges = <0 0x56000000 0x2000000>;
449 reg = <0x58000000 4>,
450 <0x58000014 4>;
453 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
460 ranges = <0 0x58000000 0x1000000>;
462 dss: dss@0 {
464 reg = <0 0x80>;
470 ranges = <0 0 0x1000000>;
474 reg = <0x1000 0x4>,
475 <0x1010 0x4>,
476 <0x1014 0x4>;
494 ranges = <0 0x1000 0x1000>;
496 dispc@0 {
498 reg = <0 0x1000>;
507 reg = <0x2000 0x4>,
508 <0x2010 0x4>,
509 <0x2014 0x4>;
522 ranges = <0 0x2000 0x1000>;
524 rfbi: encoder@0 {
525 reg = <0 0x1000>;
534 reg = <0x3000 0x4>;
540 ranges = <0 0x3000 0x1000>;
542 venc: encoder@0 {
544 reg = <0 0x1000>;
553 reg = <0x4000 0x4>,
554 <0x4010 0x4>,
555 <0x4014 0x4>;
567 ranges = <0 0x4000 0x1000>;
569 dsi1: encoder@0 {
571 reg = <0 0x200>,
572 <0x200 0x40>,
573 <0x300 0x20>;
582 #size-cells = <0>;
588 reg = <0x5000 0x4>,
589 <0x5010 0x4>,
590 <0x5014 0x4>;
602 ranges = <0 0x5000 0x1000>;
604 dsi2: encoder@0 {
606 reg = <0 0x200>,
607 <0x200 0x40>,
608 <0x300 0x20>;
617 #size-cells = <0>;
623 reg = <0x6000 0x4>,
624 <0x6010 0x4>;
638 ranges = <0 0x6000 0x2000>;
640 hdmi: encoder@0 {
642 reg = <0 0x200>,
643 <0x200 0x100>,
644 <0x300 0x100>,
645 <0x400 0x1000>;
668 reg = <0x400 0x100>;
674 reg = <0x500 0x100>;
675 #power-domain-cells = <0>;
680 reg = <0x700 0x100>;
686 reg = <0xf00 0x100>;
692 reg = <0x1b00 0x40>;
701 timer@0 {