Lines Matching full:clks
75 clocks = <&clks IMX7D_CLK_ARM>;
96 clocks = <&clks IMX7D_USB_PHY1_CLK>;
103 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
170 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
197 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
212 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
247 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
270 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
285 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
404 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
411 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
419 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
427 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
441 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
442 <&clks IMX7D_GPT1_ROOT_CLK>;
450 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
451 <&clks IMX7D_GPT2_ROOT_CLK>;
460 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
461 <&clks IMX7D_GPT3_ROOT_CLK>;
470 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
471 <&clks IMX7D_GPT4_ROOT_CLK>;
480 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
535 clocks = <&clks IMX7D_OCOTP_CLK>;
588 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
602 clocks = <&clks IMX7D_SNVS_CLK>;
610 clocks = <&clks IMX7D_SNVS_CLK>;
618 clks: clock-controller@30380000 { label
680 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
690 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
702 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
703 <&clks IMX7D_ECSPI4_ROOT_CLK>;
712 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
713 <&clks IMX7D_PWM1_ROOT_CLK>;
723 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
724 <&clks IMX7D_PWM2_ROOT_CLK>;
734 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
735 <&clks IMX7D_PWM3_ROOT_CLK>;
745 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
746 <&clks IMX7D_PWM4_ROOT_CLK>;
756 clocks = <&clks IMX7D_CLK_DUMMY>,
757 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
758 <&clks IMX7D_CLK_DUMMY>;
773 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
774 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
785 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
786 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
787 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
829 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
830 <&clks IMX7D_ECSPI1_ROOT_CLK>;
841 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
842 <&clks IMX7D_ECSPI2_ROOT_CLK>;
853 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
854 <&clks IMX7D_ECSPI3_ROOT_CLK>;
864 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
865 <&clks IMX7D_UART1_ROOT_CLK>;
875 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
876 <&clks IMX7D_UART2_ROOT_CLK>;
886 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
887 <&clks IMX7D_UART3_ROOT_CLK>;
897 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
898 <&clks IMX7D_SAI1_ROOT_CLK>,
899 <&clks IMX7D_CLK_DUMMY>,
900 <&clks IMX7D_CLK_DUMMY>;
912 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
913 <&clks IMX7D_SAI2_ROOT_CLK>,
914 <&clks IMX7D_CLK_DUMMY>,
915 <&clks IMX7D_CLK_DUMMY>;
927 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
928 <&clks IMX7D_SAI3_ROOT_CLK>,
929 <&clks IMX7D_CLK_DUMMY>,
930 <&clks IMX7D_CLK_DUMMY>;
945 clocks = <&clks IMX7D_CAAM_CLK>,
946 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
972 clocks = <&clks IMX7D_CLK_DUMMY>,
973 <&clks IMX7D_CAN1_ROOT_CLK>;
983 clocks = <&clks IMX7D_CLK_DUMMY>,
984 <&clks IMX7D_CAN2_ROOT_CLK>;
996 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1006 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1016 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1026 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1035 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1036 <&clks IMX7D_UART4_ROOT_CLK>;
1046 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1047 <&clks IMX7D_UART5_ROOT_CLK>;
1057 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1058 <&clks IMX7D_UART6_ROOT_CLK>;
1068 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1069 <&clks IMX7D_UART7_ROOT_CLK>;
1078 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1087 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1097 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1108 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1133 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1134 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1135 <&clks IMX7D_USDHC1_ROOT_CLK>;
1145 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1146 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1147 <&clks IMX7D_USDHC2_ROOT_CLK>;
1157 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1158 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1159 <&clks IMX7D_USDHC3_ROOT_CLK>;
1172 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1173 <&clks IMX7D_QSPI_ROOT_CLK>;
1182 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1183 <&clks IMX7D_SDMA_CORE_CLK>;
1197 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1198 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1199 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1200 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1201 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1221 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1232 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1233 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1238 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;